BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CERN//INDICO//EN BEGIN:VEVENT SUMMARY:FPGA and ASIC based algorithms for the present and upgraded LHCb silicon vertex detector DTSTART;VALUE=DATE-TIME:20120503T103000Z DTEND;VALUE=DATE-TIME:20120503T110000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-56@cern.ch DESCRIPTION:Speakers: Dr. SZUMLAK\, Tomasz (Glasgow University)\nThe LHCb experiment is dedicated to the search for new physics \nsignatures in beau ty and charm decays. The selection of interesting \nsignal events requires accurate measurements of decay lifetimes \nand reconstruction of complex vertex topologies. The VErtex LOcator (VELO) \nhas been designed to fulfil l these functions\, by providing tracking \ninformation close to the proto n-proton collision region. \n\nAt present analogue information from its re adout electronic is digitized\, corrected\nfor various sources of coherent noise\, and further processed through \na series of algorithms implemente d on FPGAs residing on the ìoff detectorî \nreadout boards. The tuning o f the parameters of these algorithms is performed\nusing a bit-perfect emu lation of these algorithms integrated in to the full\noff-line software of the experiment. These algorithms are described\, and their\nperformance a nd tuning in the course of the 2011 data taking cycle are summarized.\n\nF or the LHCb upgrade in addition to the evolution to the present strip desi gn\na pixel option is also being developed. In both cases the zero-suppres sion\nfunctionality will be preformed by the read out front-end chip. For this a new ASIC\nis being designed - the chip will be a derivative of the TimePix/MediPix family.\nThe chip will incorporate a local intelligence in the pixel for time over\nthreshold measurement\, time stamping and spare read out. In order to cope with\nthe data rates and use the pixel area mos t effectively an on-chip data compression\nscheme will be implemented. Thi s contribution will give an overview of the chip\ndigital architecture\, a nd describe the off-detector signal processing\, including\nthe time order ing and clustering.\n\nhttp://indico.cern.ch/contributionDisplay.py?contri bId=56&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=56&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Hybrid circuits and substrate technologies for the CMS Tracker upg rade DTSTART;VALUE=DATE-TIME:20120504T080000Z DTEND;VALUE=DATE-TIME:20120504T083000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-43@cern.ch DESCRIPTION:Speakers: BLANCHOT\, Georges (CERN)\nThe upgrade of the CMS tr acker at the HL-LHC will require the design of new front-end modules. Thes e tracker modules will embed new front-end flip-chip ASICs that will be bu mp bonded to high density substrates\, and those will be directly wire bon ded to the tracker sensors. The resulting hybrid circuits will concentrate the module data flow and feed an optical transmitter module (GBT) that wi ll be located on an adjacent service board. To achieve this degree of inte gration\, the hybrid circuits have to be designed in large formats using h igh density substrate technologies that are commonly used for integrated c ircuits packaging. The different technologies that have been identified wi ll be presented with their respective merits and constraints. Different ci rcuits arrangements will be proposed for the assembly of the module electr onics\, aiming for a cost effective and reliable manufacturability of the CMS tracker modules.\n\nhttp://indico.cern.ch/contributionDisplay.py?contr ibId=43&sessionId=2&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=43&sessionId=2& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:An innovative detection module concept for PET DTSTART;VALUE=DATE-TIME:20120503T133000Z DTEND;VALUE=DATE-TIME:20120503T140000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-60@cern.ch DESCRIPTION:Speakers: Dr. MARINO\, nahema (university and INFN pisa)\, MAR INO\, Nahema ()\, MARINO\, Nahema ()\nThe design of a positron emission to mography (PET)detection module capable of working inside a magnetic resona nt imaging (MRI) system is the main objective of the INFN 4D-MPET project. Simultaneous PET/MRI technology offers better soft tissue contrast and lo wer radiation doses by providing both functional and morphological informa tion at the same time. The detector will be based on Silicon Photomultipli ers (SiPM)\, which are magnetic field compatible\, coupled to a single LYS O scintillator crystal in order to determine the x and y coordinates on th e detector with high precision. An improved performance will be accomplis hed by measuring the Depth of Interaction (DOI) and evaluating the Time of Flight (TOF): the former information is used for decreasing the uncertain ty of the z coordinate while the latter reduces the image background noise .\nThe SiPM detectors will be laid out on both the top and bottom large sc intillator faces with respect to the incoming radiation. The two faces wil l feature identical and independent readout electronics for time and energ y measurement. Each readout system will include four identical front-end ( FE) mixed-mode ASIC’s connected to the SiPM matrices\, a cluster process or (CP) ASIC for data reduction and a laser driver/photodiode receiver/clo ck reconstruction (LD) ASIC for communication with the external data acqui sition system through fibre-optics. All ASIC’s will be mounted and wire- bonded without package and communicate each other through low voltage diff erential signalling (LVDS) pads for MRI interference reduction.\nThe front -end ASIC’s will have multiple-channels each of them reading one SiPM ou tput. Every channel will be made up of a preamplifier\, a shaper\, two dis criminators for self-triggering and a time to digital converter (TDC) with a time over threshold (TOT) feature for energy evaluation. The first disc riminator will have a fast response so as to trigger efficiently on single photo-electrons\; it will provide the starting time information to the TD C/TOT block so as to measure a time which is very close to the interaction time in the scintillator. The second discriminator will provide event val idation and TOT start/stop signals with a threshold which must be programm able between 3 and 10 photo-electrons. Such a double threshold technique i s necessary to get a high resolution (σLSB =100ps) if the SiPM intrinsic background rate of around 2MHz/mm2 is considered. If the event is valid th en the conversion can be completed and the event is transmitted to the clu ster processor. If\, on the other hand\, the high threshold is not reached within a given time window then the TDC must reset itself and wait for th e next low threshold event. Moreover\, simulations have shown that a bette r time resolution can be accomplished if the timing information from both crystal faces is used. Shaping is necessary to avoid challenging constrain ts on the stability and uniformity of the signal shape which must be used for the TOT measurement. Moreover\, the tail-linearising filter implies a lower precision requirement on the trailing edge thus reducing the readout complexity.\nThe cluster processor task will consist in reducing the amou nt of data to be sent to the external acquisition system based on a cluste ring technique. Three different clustering levels with increasing complexi ty are under investigation: the first is the time-stamp clustering\, where the cluster comprises all the channels with the same time-stamp. If the c luster energy is higher than a given threshold\, all its data is transmitt ed. The second clustering level is based on both time-stamp and spatial di stribution: in this case only one time value per cluster is transmitted\; time-stamp and spatial clustering with centroid is the third clustering op tion where the data transmission is reduced to the cluster position coordi nates (x\, y\, time and amplitude). Moreover\, clustering will be used in the evaluation of the DOI by considering the asymmetry in the cluster size on the two crystal faces.\nFinally\, the LD ASIC will be used in order to minimize the number of communication devices to one optical input plus on e optical output.\nAn active temperature control is required for the syste m so as to reduce the SiPM dark count and keep its heat dissipation as low as possible in order to avoid degradations in the electronics performance .\nFurthermore\, two modes of operation will be implemented both for pre-c linical and clinical applications.\n\nhttp://indico.cern.ch/contributionDi splay.py?contribId=60&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=60&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Introduction and logistic DTSTART;VALUE=DATE-TIME:20120503T070000Z DTEND;VALUE=DATE-TIME:20120503T073000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-61@cern.ch DESCRIPTION:Speakers: PALLA\, Fabrizio (Sezione di Pisa (IT))\nhttp://indi co.cern.ch/contributionDisplay.py?contribId=61&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=61&confId=15452 5 END:VEVENT BEGIN:VEVENT SUMMARY:Discussion DTSTART;VALUE=DATE-TIME:20120504T083000Z DTEND;VALUE=DATE-TIME:20120504T090000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-62@cern.ch DESCRIPTION:Speakers: \nhttp://indico.cern.ch/contributionDisplay.py?contr ibId=62&sessionId=2&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=62&sessionId=2& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Discussion DTSTART;VALUE=DATE-TIME:20120504T153000Z DTEND;VALUE=DATE-TIME:20120504T163000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-63@cern.ch DESCRIPTION:Speakers: \nhttp://indico.cern.ch/contributionDisplay.py?contr ibId=63&sessionId=5&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=63&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Discussion DTSTART;VALUE=DATE-TIME:20120505T100000Z DTEND;VALUE=DATE-TIME:20120505T110000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-64@cern.ch DESCRIPTION:Speakers: \nhttp://indico.cern.ch/contributionDisplay.py?contr ibId=64&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=64&sessionId=3& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Discussion DTSTART;VALUE=DATE-TIME:20120503T143000Z DTEND;VALUE=DATE-TIME:20120503T153000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-65@cern.ch DESCRIPTION:Speakers: \nhttp://indico.cern.ch/contributionDisplay.py?contr ibId=65&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=65&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Level-1 Track Trigger for CMS with double stack detectors and lo ng barrel approach DTSTART;VALUE=DATE-TIME:20120503T123000Z DTEND;VALUE=DATE-TIME:20120503T130000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-66@cern.ch DESCRIPTION:Speakers: SALVATI\, Emmanuele (Cornell University (US))\nThe u pgrade of the LHC machine is planned to deliver luminosities 5 to\n10 time s larger than the design one of 1e34 cm-2s-1. A novel tracking\nsystem for the CMS experiment must be designed and built. One main\naspect of the cu rrent activities consists in understanding the\ncapabilities that differen t designs such a tracker would have to\nprovide for the Level 1 hardware t rigger to complement the muon and\ncalorimeter information. Data rate red uction at hardware level\nconsists in both reducing multiple hits from a s ingle track and\nrejection of low Pt tracks. Pattern-based hit correlation of properly\nbuilt clusters of hits would provide quality Level 1 primiti ves to the\nhardware trigger. These can be combined together in a projecti ve\ngeometry to perform a rough tracking to be implemented online\,\nretur ning rough Pt\, direction and vertex information for a candidate\ntrack. T he benchmark results from simulations within the official CMS\nframework a re presented for one particular layout based on barrel\ntrigger layers\, e mphasizing the flexibility of this tool for the\ndesign and test of differ ent tracking strategies at level 1 to be\ncompared with the developments i n trigger architectures\nimplementation.\n\nhttp://indico.cern.ch/contribu tionDisplay.py?contribId=66&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=66&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Interconnect issues for the CMS 3-D track trigger DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-24@cern.ch DESCRIPTION:Speakers: Prof. TRIPATHI\, Mani (UC Davis)\nThe 3-D track trig ger concept being developed for the CMS upgrade involves interconnections for signals to be transmitted between various layers of sensors and readou t electronics. In this design\, the two sensitive layers are separated by an interposer\, which provides the lever arm for measuring transverse mome nta. Such an assembly would require new challenges for bump-bonding of la rge arrays. Progress in various techniques being investigated for this pur pose will be presented. Sequential bump-bonding steps using solders with different melting points will be described. Plans for achieving high yield s in assembly will be discussed.\n\nhttp://indico.cern.ch/contributionDisp lay.py?contribId=24&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=24&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A fast digital readout architecture for vertically integrated pixe l sensors DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-25@cern.ch DESCRIPTION:Speakers: Dr. GIORGI\, Filippo Maria (Universita e INFN (IT))\ nA digital architecture for fast sparsified readout has been developed for the implementation of wide 3D pixel sensors. The Italian VIPIX collaborat ion is realizing two prototypes exploiting the Tezzaron-Chartered vertical integration process in order to build a 12k-pixel 3D deep n-well MAPS sen sor\, and a 3D 4k-pixel front-end chip\, with 50 um pitch\, for a fully de pleted silicon sensor. In both cases the digital and analog circuits are i mplemented on dedicated tiers in order to reduce the digital noise inducti on and enhance the digital logic at pixel level. The dense in-pixel logic allows for innovative sparsified hit extraction techniques\, in order to r educe the pixel occupancy. The readout logic we propose can face an input hit rate of the order of 100MHz/cm2 and allows a time resolution of 100 ns \, in addition it can be configured to work in data-driven or triggered mo de. \nThe technology process is a Chartered CMOS 130 nm\, this feature siz e presents an intrinsic radiation tolerance and allow the use of foundry ’s standard cells. The architecture has been deeply investigated in term s of efficiency on a wide span of input parameters (hit rate\, time resolu tion\, trigger latency etc.) thanks to a parameterized VHDL synthesizable model\, that has been designed to match even larger matrices of pixels. Th e model was stimulated within a complex test bench environment that includ ed a Monte Carlo generator for the hit extraction\, a simulation monitor a nd a C++ framework for the efficiency analysis and error detection. The fl exibility of the code allow to easily tailor the architecture and of the t est bench on different matrix dimensions: we observed this scalable archit ecture working properly even with bigger matrices\, of the order of 50k pi xels. \nThe paper presents the readout efficiency versus a variety of para meters as the clock rate\, the pixel hit-rate and\nthe time-stamp resoluti on. The overall project leads to design a high-density thin vertex detecto r with an on-chip\nsparsified digital readout system\, for particle tracki ng\, aimed at matching the requirements of future high-energy physics\nexp eriments like SuperB.\n\nhttp://indico.cern.ch/contributionDisplay.py?cont ribId=25&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=25&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Front end intelligence for triggering and local track measurement in gaseous pixel detectors DTSTART;VALUE=DATE-TIME:20120504T133000Z DTEND;VALUE=DATE-TIME:20120504T140000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-26@cern.ch DESCRIPTION:Speakers: GROMOV\, Vladimir (NIKHEF)\nThe TimePix3 chip\, curr ently being designed\, is a pixel read-out chip with precision tdc (\n\nht tp://indico.cern.ch/contributionDisplay.py?contribId=26&sessionId=5&confId =154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=26&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A clusterization algorithm for ATLAS pixel upgrade. DTSTART;VALUE=DATE-TIME:20120505T063000Z DTEND;VALUE=DATE-TIME:20120505T070000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-27@cern.ch DESCRIPTION:Speakers: TODOROV\, Teddy (Centre National de la Recherche Sci entifique (FR))\nThe increase in the LHC luminosity and the reduction of t he pixel size foreseen for the ATLAS pixel upgrade leads to an increased a mount of data generated by the pixel detector at each beam crossing.\nThe bandwidth of the readout should be upgraded to deal with this increase of data\, to keep a good detector efficiency.\nAnother approach\, studied at LAPP\, consists in decreasing the amount of data\, by grouping adjacent pi xels\, thus forming clusters on the read-out chip. The analog center of gr avity of the cluster can be determined directly inside the readout ASIC\, and cluster can be classified at an early stage as "high Pt MIP-compatible " or not. Only the first category contains precise position information of interest to the tracking\, and requires digitizing the barycenter positio n. The clusters in the second category contain only topological informatio n and do not require digitization.\nIn addition to the data reduction\, th e early availability of cluster positions of high Pt tracks can speed up t rigger algorithms\,\nThe implementation of the local clustering algorithm takes advantage of TEZZARON 130nm 3D electronics\, with analog readout of pixel\, but it can also be applied to deep submicron 2D technology such 65 nm.\nThe architecture will be detailed and the bandwidth will be compared to the one of more classical approach readout electronics.\n\nhttp://indi co.cern.ch/contributionDisplay.py?contribId=27&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=27&sessionId=3& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Multi_Gigabit wireless data transfer at 60 GHz DTSTART;VALUE=DATE-TIME:20120504T143000Z DTEND;VALUE=DATE-TIME:20120504T150000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-20@cern.ch DESCRIPTION:Speakers: Mr. SOLTVEIT\, Hans Kristian (Ruprecht-Karls-Univers itaet Heidelberg (DE))\nThe data transfer rate from highly granular tracki ng detectors are limited today by the available bandwidth in the readout links what prevents the detectors to be used for fast triggering.\n\nMMwav e technology is the next generation wireless technology that can provide m ulti-Gbps wireless connectivity for short distances between electronics [1 ]. Since the carrier frequency is higher (60 GHz)\, more data can be sent in a given period of time\, by modulating the carriers amplitude\, frequen cy or phase. The 60 GHz unlicensed frequency band is of particular interes t for indoor point-to-point multi-gigabit due to its very low atmospheric attenuation and the large amount of spectral bandwidth (7-9 GHz). With suc h a bandwidth available and the optimum choice of modulation scheme\, it w ould be possible to achieve a data rate in the 10’s of Gbps\, and could therefore be a suitable method to solve the data transfer rate problem. F urthermore\, due to its small wave lengths at carrier frequency of 60 GHz (5mm)\, it becomes possible to integrate the antenna on-chip or in-packag e.\nThe narrow beams of millimeter wave also allow for deployment of multi ple independent links in close proximity. That makes the wireless modules very suitable to pass data between tracking layers.\nThe high speed links are low mass\, low power\, more secure and does not interfere with other w ireless technologies for short distance data transfer. \n\nIn this context a multi-Gigabit wireless readout chip operating in the 60 GHz region is c urrently under development at the University of Heidelberg. The design is based on the well known superheterodyne transceiver architecture with appr oximately 3Gb/s throughput\, x mW transmit power\, 5 dB receiver noise fig ure (NF) and high gain omni-directional antennas. With such specification s\, the link budget calculation shows that a range of few meters is possib le. The targeted data rate for our first prototype is 3Gbps.\n\nIn this ta lk the key building blocks necessary to realize this architecture will be described.\nSilicon-Germanium (SiGe) Heterojunction Bipolar Transistors (H BTs) BiCMOS is chosen as the technology to demonstrate the concept. In add ition\, we will also report on the current status of the design and perfor mance obtained in simulation of our Millimeter Wave Chip development for a possible upgrade of the ATLAS Fast Tracker\, in terms of area\, estimated power consumption\, data rate\, and the emerging 3-D technology implement ation scenarios that is particularly beneficial for 3-D wireless chip deve lopment.\n\n[1] R. Brenner. “Multigigabit wireless transfer of trigger data through millimetre wave technology”.\n 2010 JINST 5 c07002\n\ nhttp://indico.cern.ch/contributionDisplay.py?contribId=20&sessionId=5&con fId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=20&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Micro-channel cooling for pixel detectors DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-58@cern.ch DESCRIPTION:Speakers: BOSI\, Filippo (INFN Pisa)\nIn HEP experiments the u se of pixel detectors requires that high power density in the sensitive a rea (up to 2 W/cm2) should be carried away by efficient thermal systems\, eventually integrated in the light mechanical support structures. \nThe m icro-channel cooling technology is featured by a highly efficient thermal exchange and it can profit by the miniaturization technique applied on co mposite materials. Thus a viable solution based on microchannel can be pr ovide both for the thermal and mechanical structure of a silicon module. \ nWe present the latest progress on the development of mechanical supports with microchannel cooling for pixel detector systems\, designed in particu lar to match the specifications of the most internal layer of the Silicon Vertex Tracker of the Super-B experiment.\nThe low-material budget prototy pes have thickness of 0.11 % X0 and the results of the characterization t ests performed at the thermal-fluid-dynamic facility of the INFN Pisa are reported.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=58&ses sionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=58&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Asynchronous readout architectures for Tracker Front-End ASICs DTSTART;VALUE=DATE-TIME:20120504T100000Z DTEND;VALUE=DATE-TIME:20120504T103000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-48@cern.ch DESCRIPTION:Speakers: Dr. JOHNSON\, Marvin (Fermilab)\, JOHNSON\, Marvin ( Fermi National Accelerator Lab. (US))\nWe preset a design of a front end A SIC that combines a level 1\ntrigger and normal event readout. It uses as ynchronous logic through\nout the design to reduce both power consumption and noise sensitivity.\nThe only clock used is the 40 MHz LHC clock. A te st chip based on\nthis design is planned to be submitted in July of this y ear.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=48&sessionI d=5&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=48&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:The ultra low mass cooling system of the Belle II DEPFET detector DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-23@cern.ch DESCRIPTION:Speakers: Dr. MARINAS PARDO\, Carlos (Bonn University)\nThe ne w e$^{+}$e$^{-}$ colliders impose unprecedented demands to the performance of the vertex detectors. To achieve the required resolution in the vertex reconstruction\, besides highly segmented pixel detectors\, the material budget has to be kept at very low levels to reduce the multiple Coulomb sc attering. These requirements are even more challenging in the case of the new Japanese Super Flavour Factory (SuperKEKB) where the very low momentum of the particles in the final state requires a vertex detector with less than 0.2%~X$_{0}$ per layer\, together with 50x50~$\\mu$m$^{2}$ pixels\, t o achieve the aimed resolution of 8.5~$\\mu$m.\n\nAs a consequence\, there is an obvious impact on the cooling system\, that has to be carefully des igned\, not allowing active cooling pipes inside the acceptance region. Du e to the low power dissipation of the DEPFET sensor and the special geomet ry of the detectors (with the front end electronics placed at both ends of the ladder)\, the system can be chilled using 2-phase CO$_{2}$ cooling th rough the massive support structures outside of the acceptance\, while the sensitive area relies on forced convection with cold dry air.\n\nIn the t alk not only full thermal simulations will be presented but also measureme nts done with a real mock up\, showing that a proper cooling of the vertex detector can be made using this approach.\n\nhttp://indico.cern.ch/contri butionDisplay.py?contribId=23&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=23&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Self Seeded First Level Track Trigger for ATLAS DTSTART;VALUE=DATE-TIME:20120505T070000Z DTEND;VALUE=DATE-TIME:20120505T073000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-46@cern.ch DESCRIPTION:Speakers: SCHOENING\, Andre (Physikalisches Institut-Ruprecht- Karls-Universitaet Heidelberg-U)\, SCHMITT\, Sebastian (Ruprecht-Karls-Uni versitaet Heidelberg (DE))\nFor the planned high luminosity upgrade of the Large Hadron Collider\, \naiming to increase the instantaneous luminosity to 5-7 x 10^34/cm^2/s\,\nthe implementation of a first level track trigge r has been proposed\,\nwhich could be installed in the year 2020/21 along with the complete \nrenewal of the ATLAS Inner Detector.\nThe fast readout of the hit information from the Inner Detector is \nconsidered as main ch allenge of such a track trigger. Different \nconcepts for the implementati on of a first level trigger are currently \nstudied within the ATLAS colla boration.\nThe so called "Self Seeded" track trigger concept exploits fas t \nfront-end filtering algorithms based on cluster size reconstruction \n and fast vector tracking to select hits associated to high momentum \ntrac ks. Simulation studies have been performed and results on \nefficiencies a nd expected bandwidth reductions are presented for\ndifferent layouts.\n\n Possible hardware implementations of the first level track processor\nable to reconstruct all high momentum tracks in every collision within a laten cy of 1 mus will be discussed.\n\nhttp://indico.cern.ch/contributionDispla y.py?contribId=46&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=46&sessionId=3& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Status of Work on Vertically Integrated Circuits DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-47@cern.ch DESCRIPTION:Speakers: DEPTUCH\, Grzegorz (FERMILAB)\nCommencing work on th e 3D-integrated circuits in the High Energy Physics (HEP) community\, whic h coincided with the appearance at the same time of first commercial 3D-IC design kits\, whetted the appetite of the community and raised confidence in the rapid rollout of 3D-IC technology\, which undoubtedly introduces a new quality to integrated readout system for the detectors. The Fermilab team was in this group of a few\, who spearheaded the development of 3D in tegrated circuits for detector's readout. At the first place a proprietary fully-depleted CMOS SOI process by MIT-LL and the via-last based wafer bo nding technology was used. Commercial bulk CMOS wafers with front-end-of-l ine integrated micrometers-size through silicon vias (TSVs) and the Tezzar on wafer bonding technology was used at the later time. The early Fermilab work led to the formation of an international consortium\, grouping major research centers\, for the development of vertically integrated circuits. The consortium submitted the first multi project wafer (MPW) run to Tezza ron with over 25 different designs in 2009. The run unfortunately has been suffering from multiple problems causing an overall delay to such an exte nt that no diced 3D parts could be delivered to the participants until the drafting of this abstract. Despite of this downbeat of the apparent pictu re of the state of the first HEP MPW run\, it is received as the source of learning experiences\, about 3D-IC processing technology and its crucial ingredients\, like requirements for the surface flatness and surface treat ment\, alignment\, gas atmosphere\, etc. Due to the use up of initial stoc ks of wafers for failed attempts of bonding\, it was necessary to start an additional lot of wafers at the foundry. By having the conditions of the bonding process fine-tuned\, it is expected that the wafers will eventuall y be bonded successfully\, resulting in distribution of chips for testing. The review of consecutive steps undertaken with Tezzaron\, illustrated by their results\, will be provided at the presentation. In the autumn of la st year\, a group of professional brokers (MOSIS/CMP/CMC) decided to open an access to the Tezzaron/GlobalFoundries 3D-IC process through the MOSIS MPW scheme. The decision drew deeply from the knowledge acquired in the co mpletion of the 3D-IC MPW run by Fermilab and nonetheless existing positiv e experience of full processing of another MPW run (parallel to the HEP on e) by Tezzaron. New high density circuit bonding techniques\, wafer thinni ng\, and submicrometer size TSVs allowing connection to top and bottom sid es of an IC provide new opportunities for the detector designer. These opp ortunities will be presented by looking at various 3D designs that have be en completed for the MPW run or are being planned for exploration.\n\nhttp ://indico.cern.ch/contributionDisplay.py?contribId=47&sessionId=6&confId=1 54525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=47&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Radiation tolerant IP-cores for the control and readout of Front-E nd electronics in future Silicon detectors DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-45@cern.ch DESCRIPTION:Speakers: MAGAZZU\, Guido (Univ. of California Santa Barbara ( US))\nThe FF-LYNX protocol represents an innovative and flexible solution for the distribution of Timing\, Trigger and Control (TTC) signals and the data readout in future detectors for the High Energy Physics. Transmitter (TX) and Receiver (RX) interfaces to serial electrical links implementing the FF-LYNX protocol with different speed options (160Mbps\, 320Mbps\, 64 0Mbps) have been developed. They are available as VHDL cores for integrati on in commercial FPGA devices and as Standard-Cell based cores\, designed and developed in the IBM CMOS 130nm technology. Architecture and behavior of the interfaces and results of test and characterization of the prototyp es embedded in the test ASICs fabricated in 2011 will be presented. \n\nRa diation tolerant FIFOs have been developed as input and output buffers in TX and RX interfaces. They are available as stand-alone IP-cores and can b e used in Front-End ASICs or other circuits where radiation tolerant data buffers are required. Architecture and behavior of these FIFO blocks will be described as well as results of irradiation tests performed on the thei r prototypes. \n \nResults of tests performed with FF-LYNX Encoder and De coder directly coupled with the GBT Transmitter and Receiver in an FPGA pr oof-of-concept demonstrator of optical links handled by GBT transceivers a nd running data encoded with the FF-LYNX protocol will be presented as wel l as the architecture and the behavior of the Data Concentrator Module\, a VHDL core that merges input data transmitted from multiple sources throug h “low-speed” serial links into one (or more) “high-speed” output serial links. \n\nFinally future plans\, mainly focused on the development of interfaces with improved speed and power performances and including cu stom Serializer and Deserializer modules will be presented.\n\nhttp://indi co.cern.ch/contributionDisplay.py?contribId=45&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=45&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Use of Associative Memories for L1 triggering in LHC environment. DTSTART;VALUE=DATE-TIME:20120505T073000Z DTEND;VALUE=DATE-TIME:20120505T080000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-42@cern.ch DESCRIPTION:Speakers: MAGALOTTI\, Daniel (INFN Sezione Perugia (IT))\nMode rn high energy physics experiments search for extremely rare processes hid den in much larger background levels. As the experiment complexity\, the a ccelerator backgrounds and luminosity increase we need increasingly exclus ive selections to efficiently select the rare events inside the huge backg round.\nIn the framework of the CMS experiment at LHC one of the identifie d challenges for future upgrade is the capability of using the tracker inf ormation to trigger events already at L1 (now they are used at L2). \nThis strategy requires massive computing power to minimize the online executio n time of complex tracking algorithms and the “combinatorial challenge ”.\nAssociative Memories (AM) have been already used in other experiment s (CDF) as a way to compare the tracker informations of each event to pre- calculated “expectations” (pattern matching) in a very short time and contribute to the trigger decision. To use the AM approach for the CMS tra cker one of the main challenges is to make available the tracker data to t he AM processor in a very short time (6 s is the L1 latency for CMS). \ n\nWe describe a possible application of AM in the CMS environment using t he existing hardware developed for other experiments\, the AMBslim mother board consisting of 4 smaller boards\, the Local Associative Memory Banks (LAMB)\, each hosting 32 AM chips to contain the stored patterns with the readout logic. The ability of a single AMBSlim to process a single event i s much less than the amount of input data foreseen for the CMS case\, and the latency strongly depends on the time necessary to load the data in the AM system and to process a single event.\nOne possible solution is to par allelize the event processing inside the AMBslim board assigning each even t to one LAMB. We describe the firmware implementation of this concept in the current hardware and the results obtained.\n\nFinally we discuss a pos sible modification of the LAMB hardware in order to obtain the minimum del ay time for processing events.\n\nhttp://indico.cern.ch/contributionDispla y.py?contribId=42&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=42&sessionId=3& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC\, using a nested well structure to decouple the detector from the electroni cs DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-29@cern.ch DESCRIPTION:Speakers: KHALID\, Farah (F)\nMonolithic Active Matrix with Bi nary Counters (MAMBO) IV ASIC has been designed for detecting and measurin g low energy X-rays from 6-12keV. A nested well structure with a buried n- well (BNW) and a deeper buried p-well (BPW) is used to electrically isolat e the detector from the electronics. BNW acts as an AC ground to electrica l signals and behaves as a shield. BPW creates a homogenous electric field in the entire detector volume. The ASIC consists of a matrix of 41×42 pi xels\, each of 105x105µm2. Each pixel contains analogue functionality acc omplished by a charge preamplifier\, CR-RC2 Shaper and a baseline restorer . It also contains a window comparator with Upper and Lower thresholds whi ch can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a sh ift register to serially output the data from the entire ASIC.\n\nhttp://i ndico.cern.ch/contributionDisplay.py?contribId=29&sessionId=6&confId=15452 5 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=29&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:From hybrids pixels to smart vertex detectors using 3D technologie s DTSTART;VALUE=DATE-TIME:20120504T063000Z DTEND;VALUE=DATE-TIME:20120504T070000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-40@cern.ch DESCRIPTION:Speakers: CLEMENS\, JCC (Universite d'Aix - Marseille II (FR)) \nEven if 3D electronics suffers difficult beginnings\, industrial trends are now strongly pushing that way to a production phase. Keeping in mind t he usual arguments of power consumption\, speed\, technology mixing\, new and less expected possibilities are now appearing.\nIn trackers world\, f ew attempts have been made to introduce 3D not only as an alternative to s hrinking technologies but also as a source of new possibilities.\nPost-pro cessed TSV have yet proven to be feasible in HEP circuits allowing for ne w routing schemes of circuits IO without modifying the original process. O n the other hand\, 3D structures as part as the chip process offers more possibilities but the price to pay is the poor commercial offers.\nWith ne w ideas for building depleted sensors with standard MOS process\, 3D tech could allow a fully integrated fabrication of future vertex chips (sensor + read-out) in the same production chain.\nThis talk will try to give an i dea of the efforts made and of the results obtained using these 3D techniq ues in the scope of HL LHC R&D programs (ATLAS)\n\nhttp://indico.cern.ch/c ontributionDisplay.py?contribId=40&sessionId=2&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=40&sessionId=2& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A hybrid module architecture for a prompt momentum discriminating tracker at HL-LHC DTSTART;VALUE=DATE-TIME:20120503T130000Z DTEND;VALUE=DATE-TIME:20120503T133000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-41@cern.ch DESCRIPTION:Speakers: ABBANEO\, Duccio (CERN)\nThe capability of performin g quick recognition of particles with high transverse momentum (more than a few GeV/c) in the inner tracker is deemed essential to keep the CMS trig ger rate at an acceptable level at a higher luminosity LHC (L > 10^34 cm-2 s-1). We present an architecture for a novel tracking module based on a c ombination of a pixelated sensor with a short strip sensor that would offe r such capability. The critical aspects of the design such as the projecte d power consumption\, the resulting material budget\, and the data flow mo del are discussed and estimates are given. It is also shown that a manufac turable module of this type is well within the capabilities of currently a vailable microelectronic and packaging-assembly technologies.\n\nhttp://in dico.cern.ch/contributionDisplay.py?contribId=41&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=41&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A tracker for the novel mu3e experiment based on high voltage mono lithic active pixel sensors DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-1@cern.ch DESCRIPTION:Speakers: WIEDNER\, Dirk (Ruprecht-Karls-Universitaet Heidelbe rg (DE))\nThe proposed mu3e experiment will study the lepton flavor violat ing decay mu->eee which is strongly (10^-50) suppressed in the standard mo del\, but enhanced to observable levels in many models for new physics. In order to achieve the proposed branching ratio sensitivity of 10^-16 the d etector has to have high rate capability and good background suppression\, which in turn requires excellent momentum and vertex resolution. \n\nThe mu3e detector consists of two double layers of high voltage monolithic act ive pixel sensors (HV-MAPS) around a target double cone. To minimize multi ple scattering of the low energetic decay electrons (\n\nhttp://indico.cer n.ch/contributionDisplay.py?contribId=1&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=1&sessionId=6&c onfId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Nanosecond Timing Resolution with the APV25 DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-4@cern.ch DESCRIPTION:Speakers: Dr. FRIEDL\, Markus (Austrian Academy of Sciences (A T))\nIn an environment with high occupancy and continuous collisions\, con ventional readout of silicon strip detectors will lead to ambiguities in t he time domain. This problem can in principle be minimized by reducing the shaping time\, but that approach is limited by the noise penalty.\n\nThe APV25 chip\, originally developed for the CMS experiment\, includes an on- chip switched capacitor filter performing a ``deconvolution'' on three con secutive samples of the shaped signal in order to narrow down the signal t o a single bunch crossing.\nUnfortunately\, this feature requires clock sy nchronous beam and thus cannot be used in case of quasi-continuous collisi ons which will occur in the future Belle II experiment at KEK (Japan). Non etheless\, multiple samples along the shaper output can be processed outsi de of the APV25 in order to determine both peak amplitude and timing of th e sampled signal regardless of the asynchronous relation between particle and sampling\, achieving a time resolution of a few nanoseconds. Moreover\ , the data processing can be performed in real-time using look-up tables i n an FPGA. This allows comparing the timing of each hit to the trigger tim ing and discarding off-time background immediately\, saving bandwidth\, pr ocessing power and storage capacity in the subsequent DAQ.\n\nApart from t he hit time finding\, the future readout module for the Belle II Silicon V ertex Detector will also perform pedestal subtraction\, common mode correc tion and zero suppression by FPGA firmware. In addition\, the incoming ana log data will be conditioned by a digital FIR filter. We will present the concept\, existing prototypes\, results from several beam tests on various (mostly double-sided) silicon strip detectors and what is under construct ion for the Belle II experiment.\n\nhttp://indico.cern.ch/contributionDisp lay.py?contribId=4&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=4&sessionId=6&c onfId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Instrumentation of a track trigger with double buffer front-end a rchitecture DTSTART;VALUE=DATE-TIME:20120503T100000Z DTEND;VALUE=DATE-TIME:20120503T103000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-7@cern.ch DESCRIPTION:Speakers: WARDROPE\, David (University College London (UK))\nT he planned high luminosity upgrade for the LHC (SLHC)\, will increase the collision rate in the ATLAS detector by approximately a factor 5 beyond the present LHC design goal\, while also increasing the number of pile-up collisions in each event by a similar factor. This means that \nthe level -1 trigger must achieve a higher rejection factor in a more difficult env ironment. We describe a possible design which splits the level-1 trigger into a two-level system\, where the first level\, using only calorimetry and muon chambers\, defines regions of interest in the tracker \nfrom whic h to extract information for a second\, refined trigger. The use of a two- buffer front-end architecture will allow a significantly longer decision time to move data off the detector keeping the data bandwidth and buffer sizes moderate. We will describe the implementation of the scheme in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds\, rejection\, bandwidth and trigger latency will be shown and compared with the present requirements for SLHC upgrade in ATLAS.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=7&ses sionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=7&sessionId=1&c onfId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:3D Vertical Integration Technology for Fast Pattern Recognition DTSTART;VALUE=DATE-TIME:20120505T090000Z DTEND;VALUE=DATE-TIME:20120505T093000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-6@cern.ch DESCRIPTION:Speakers: LIU\, Tiehui Ted (Fermilab)\nHardware-based pattern recognition for fast triggering on particle tracks has been successfully u sed in high-energy physics experiments for some time. The CDF Silicon Vert ex Trigger (SVT) at the Fermilab Tevatron is an excellent example. The met hod used there\, developed in the 1990’s at Pisa\, is based on algorithm s that use a massively parallel associative memory architecture to identif y patterns efficiently at high speed. However\, due to much higher occupan cy and event rates at the LHC\, and the fact that the LHC detectors have a much larger number of channels in their tracking detectors\, there is an enormous challenge in implementing fast pattern recognition for a track tr igger\, requiring about three orders of magnitude more associative memory patterns than what was implemented in the original CDF SVT. Scaling of cur rent technologies is unlikely to satisfy the scientific needs of the futur e\, and investments in transformational new technologies need to be made. As Moore’s law is approaching severe limitations\, it is expected that 3 D Vertical Integration Technology will be the next scaling engine. More im portantly\, in certain cases\, the 3D technology also provides novel desig n opportunities that are simply not possible in 2D and this is the case fo r fast pattern recognition\, such as the associative memory approach. In t his talk\, we will present a new concept of using the emerging 3D vertical integration technology to significantly advance the state-of-the-art for fast pattern recognition within and outside HEP. A R&D collaboration based on this concept is being developed and the status of this R&D project as well as the future direction will be presented as well.\n\nhttp://indico.c ern.ch/contributionDisplay.py?contribId=6&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=6&sessionId=3&c onfId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Fast Clustering Block for Silicon Strip Seeded Track Trigger DTSTART;VALUE=DATE-TIME:20120504T130000Z DTEND;VALUE=DATE-TIME:20120504T133000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-9@cern.ch DESCRIPTION:Speakers: Mr. NEWCOMER\, Mitch (University of Pennsylvania)\nA viable seeded track trigger for a high rate collider detector environment must have excellent angular precision\, response times commensurate with beam crossing rate and low mass. We have designed a fast clustering blo ck servicing 128 contiguous strips to be included in an LHC upgrade silici on strip readout ASIC with these objectives in mind. The block is based on the presence of an analog front end with binary (threshold determined) strip readout latched at each beam crossing. Combinatorial logic tests fo r the presence of one or two adjacent strips over threshold\, a cluster\, at each beam crossing and records the seven bit address of up to two clus ters via a high speed LVDS output. A correlator chip receives this data and looks for coincident hits between silicon strip layers. Since the cl ustering output will report the presence of one or two hit strips\, a half strip width (~40um) resolution may be possible for each cluster. Our re sults show that the combinatorial clustering logic will settle within 6ns. Assuming a beam crossing rate of 40MHz\, serialized data shifted out at 640MHz will meet the required beam synchronous update rate so that the cor relator chip will receive cluster information delayed by a fixed offset of only two beam crossings. Present power estimates suggest that the fast c luster block with LVDS driver will consume less than 20mW.\n\nhttp://indic o.cern.ch/contributionDisplay.py?contribId=9&sessionId=5&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=9&sessionId=5&c onfId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A real-time clustering ASIC for the PXD in Belle II DTSTART;VALUE=DATE-TIME:20120504T103000Z DTEND;VALUE=DATE-TIME:20120504T110000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-8@cern.ch DESCRIPTION:Speakers: WASSATSCH\, Andreas (MPI Physik / HLL)\nThe grouping of data elements based on characteristic relations is known as clustering .\nIt can either be used for data compression in a DAQ chain\, or even to calculate the characteristic trigger input values ​​based on event dat a.\nDriven by the requirements of the PXD detector in the Belle II experim ent @KEK/Japan\, a real-time clustering engine was developed.\nThis softwa re-inspired hardware architecture is by a pipelined structure able to perf orm up to 50k times per second the full 2D clustering of the zero-suppress ed data out of a detector array with 768x250 pixels with a up to 3% fill r ate and only one frame latency.\nDue to the scalable architecture of the c lustering core\, the engine can\nbe easily adapted to the specific needs o f other target applications\,\neven to 3D or higher dimensional operation. \nA first test chip in TSMC 65nm process technology is back from the produ ction and goes now in initial tests.\n\nhttp://indico.cern.ch/contribution Display.py?contribId=8&sessionId=5&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=8&sessionId=5&c onfId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:MCM-D Technology for Silicon Strip Frontend Hybrids DTSTART;VALUE=DATE-TIME:20120504T073000Z DTEND;VALUE=DATE-TIME:20120504T080000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-18@cern.ch DESCRIPTION:Speakers: EKLUND\, Lars (University of Glasgow (GB))\nMulti-ch ip Modules - Deposited (MCM-D) technology can be applied to\nsilicon strip modules and promises advantages in terms of integration\ncomplexity and m aterial budget. The principle is to deposit\nalternating dielectric and me tal layers directly on the silicon\nsensor\, building up a PCB like struct ure. With lithographic techniques\ntraces and vias are etched with high re solution creating a circuit\nreplacing the pitch adaptor\, wire bonds and electronics hybrid. \n\nThis paper reports on a feasibility study performe d in the context of\nthe Atlas Upgrade. The technology was evaluated in tw o prototype\nprocessing runs. The first prototypes had a single dielectric and\nmetal layer deposited on a silicon strip sensor\, with the purpose o f\nevaluating the change in performance due to the post-processing and\nth e presence of a ground plane. Sensor parameters were measured before\nand after irradiation up to 10^16 n_eq/cm^2 and charge collection\nefficiency was measured for several doses. A non-irradiated sensor was\nmeasured in a beam test yielding signal height and resolution for\nregions with and wit hout ground plane. The second prototype was a fully\nfunctional 20-chip fr ont-end hybrid with five metal layers build on a\nblank silicon sensor. Th e hybrid has the same performance as an\nidentical circuit built in kapton technology.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=18& sessionId=2&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=18&sessionId=2& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Level-1 Tracking Trigger for the CMS Upgrade using stacked silic on strip detectors and advanced pattern recognition technologies DTSTART;VALUE=DATE-TIME:20120503T080000Z DTEND;VALUE=DATE-TIME:20120503T083000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-49@cern.ch DESCRIPTION:Speakers: BOUDOUL\, Gaelle (Universite Claude Bernard-Lyon I ( FR))\, BOUDOUL\, Gaelle (Universite Claude Bernard-Lyon I (FR))\nExperienc e at high luminosity hadrons collider experiments shows that tracking info rmation enhances the trigger rejection capabilities while retaining high e fficiency for interesting physics events. The design of a tracking based t rigger for the High Luminosity LHC (HL-LHC) is an extremely challenging ta sk\, and requires the identification of high-momentum particle tracks as a part of the Level 1 Trigger. Simulation studies show that this can be ach ieved by correlating hits on two closely spaced silicon strip sensors\, an d reconstructing tracks at L1 by employing an Associative Memory approach. The progresses on the design and development of this micro-strip stacked prototype modules and the performance of few prototype detectors will be p resented. Preliminary results of a simulated tracker layout equipped with stacked modules are discussed in terms of pT resolution and triggering cap abilities. Finally\, a discussion on the L1 architecture will be given.\n\ nhttp://indico.cern.ch/contributionDisplay.py?contribId=49&sessionId=1&con fId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=49&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Low Mass On-chip Readout Scheme for Double-sided Silicon Strip D etectors DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-13@cern.ch DESCRIPTION:Speakers: Mr. IRMLER\, Christian (HEPHY Vienna)\nB-factories l ike the KEK-B in Tsukuba\, Japan\, operate at relatively low energies and thus require detectors with very low material budget inside the sensitive volume in order to minimize multiple scattering. On the other hand\, front -end chips with short shaping time like the APV25 have to be placed as clo se to the sensor strips as possible to avoid excessive noise\, which is ma inly caused by the capacitive load of the input amplifiers.\nIn order to a chieve both - minimal material budget and low noise - we developed a reado ut scheme for double-sided silicon detectors\, where the APV25 chips are p laced on a single flexible circuit\, which is glued onto the sensor. While the top-side strips are directly connected to the chips by wire-bonding a nd a small pitch adapter\, those of the bottom-side are attached by two fl exible circuits\, which are bent around the edge of the sensor. \nThis so- called “Origami” design will be utilized to build the Silicon Vertex D etector of the future Belle II experiment\, which will consist of 4 layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two carbon fiber reinforced ribs\, with a very light-weight Airex styrofoam core.\nPlacing the readout chip o nto the sensor also requires sufficient cooling\, which will be done by a highly efficient two-phase CO2 system. Thanks to the Origami concept\, all APV chips inside the active Volume are aligned in a row and thus can be c ooled by a single thin cooling pipe per ladder.\nWe will present the conce pt and the assembly procedure of the Origami chip-on-sensor modules\, and show results of beam tests which were performed at CERN on prototype modul es.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=13&sessionId =6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=13&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:The Two 3Ds Combined: Tiles for Large Area Intelligent Arrays DTSTART;VALUE=DATE-TIME:20120504T070000Z DTEND;VALUE=DATE-TIME:20120504T073000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-15@cern.ch DESCRIPTION:Speakers: JOHNSON\, Marvin (Fermi National Accelerator Lab.)\, Dr. LIPTON\, Ronald (Fermi National Accelerator Lab. (US))\nFuture intell igent tracking systems are likely to require large area sensor modules wit h\nfinely segmented\, intelligent readout. However conventional module co nstruction\, with\nreadout bonded at the periphery and significant sensor dead area\, makes it difficult\nto build large area pixelated modules with good yield\,low mass and small dead area. The\ncombination of 3D active edge sensors and 3D (vertically integrated) electronics solves these\nprob lems by enabling the fabrication of readout chip/sensor tiles which can be butted on four \nsides and are readout through the top surface. We descri be the concept for these "large area\narray" tiles and the design of activ e edge sensors and test modules currently being fabricated.\nWe describe a pplications for the CMS Track Trigger as well as vertex detectors for\nfut ure lepton colliders.\n\nhttp://indico.cern.ch/contributionDisplay.py?cont ribId=15&sessionId=2&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=15&sessionId=2& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:3D Monolithically Stacked CMOS Active Pixel Sensor Detectors for P article Tracking Applications. DTSTART;VALUE=DATE-TIME:20120503T160000Z DTEND;VALUE=DATE-TIME:20120503T163000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-14@cern.ch DESCRIPTION:Speakers: Dr. PASSERI\, Daniele (University of Perugia)\nTypic al tracking systems for particle trajectory reconstruction in High Energy Physics experiments are based on different separated sensing layers\, feat uring pixels and/or strips sensitive elements.\n\nIn this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sen sors layers\, monolithically integrated in a all-in-one chip featuring mul tiple\, stacked\, fully functional detector layers capable to provide mome ntum measurement (particle impact point and direction) within a single det ector. This will results in a very low material detector\, thus dramatical ly reducing multiple scattering issues.\n\nTo this purpose\, we rely on th e capabilities of the CMOS vertical scale integration (3D IC) technology. The chip prototype has been fabricated within a multi-project run using a 130nm CMOS Chartered/Tezzaron technology [1]\, featuring two layers bonded face-to-face (Fig. 1). Several test structures have been integrated\, nam ely single pixels\, as well as small matrices\, e.g. featuring 5x5 and 16x 16 pixels. Each pixel is 10x10 micrometers\, with different sensitive elem ent (photodiode) dimensions.\n\nTests have been carried out both on single sided (single tier) detectors (2D) and on full 3D structures\, providing the functionalities of both tiers. To this purpose\, laser scans have been carried out using highly focussed spot size (below two micrometers at 780 nm and 531nm wavelengths)\, obtaining coincidence responses of the two lay ers (Fig. 2). Tests have been made as well with X-ray sources an on the el ectrons/positrons Beam Test Facilities at the INFN LNF Frascati (Rome)\, I taly.\n\n[1] 3DIC Consortium http://3dic.fnal.gov/\n\nhttp://indico.cern.c h/contributionDisplay.py?contribId=14&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=14&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Modulator Based High Bandwidth Optical Links for HEP Experiments DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-11@cern.ch DESCRIPTION:Speakers: UNDERWOOD\, David (Argonne National Laboratory (US)) \, STANEK\, Bob (Argonne National Laboratory (US))\, Dr. FERNANDO\, Waruna (Argonne National Laboratory)\nOptical links will be an integral part of intelligent tracking systems at various scales from coupled sensors throug h intra-module and off detector communication. These links will be parti cularly useful if they utilize light modulators which are very small\, low power \, high bandwidth\, and are very rad-hard. \n\n Because of con cern with the reliability\, bandwidth\, power\, and mass of future optical links in LHC experiments\, we are investigating the use of CW lasers ext ernal to the tracking\, along with light modulators at the detector\, as a n alternative to VCSELs.\n\n We have constructed a test system with 3 suc h links\, each operating at 10 Gb/s. We present the quality of these li nks (jitter\, rise and fall time) and eye mask margins (10GbE) for 3 diffe rent types of modulators: \nLiNbO3-based\, InP-based\, and Si-based. \n\n We present the results of radiation hardness measurements with up to ~10 ^12 protons/cm^2 and ~65 krad total ionizing dose (TID)\, confirming no si ngle event effects (SEE) at 10Gb/s with all 3 types of modulators.\n\n In addition we present results on free space data links\, utilizing \nsteeri ng by MEMS mirrors and optical feedback paths for the control loop. Laser\ , modulator\, and lens systems used are described\, as well as two differe nt electronic systems for a free space steering feedback loop. Results at 10 Gb/s are shown.\n\nSome future developments of optical modulator-based high bandwidth \noptical readout systems\, and applications based on both fiber and \nfree space data links\, such as local triggering and data read out \nand trigger-clock distribution\, are also discussed.\n\nhttp://indic o.cern.ch/contributionDisplay.py?contribId=11&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=11&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Application for front end intelligence in gaseous pixel detectors for triggering DTSTART;VALUE=DATE-TIME:20120503T093000Z DTEND;VALUE=DATE-TIME:20120503T100000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-10@cern.ch DESCRIPTION:Speakers: Dr. HESSEY\, Nigel (NIKHEF (NL))\nThe combination of gaseous detectors with pixel readout chips gives unprecedented hit resolu tion (improving from O(100 um) for wire chambers to 10 um)\, as well as hi gh-rate capability\, low radiation length and giving in addition angular i nformation on the local track. These devices measure individually every el ectron liberated by the passage of a charged particle\, leading to a large quantity of data to be read out. Typically an external trigger is used to start the read-out.\n\nWe are investigating the addition of local intelli gence to the pixel read-out chip. A first level of processing detects the passage of a particle through the gas volume\, and accurately determines t he time of passage. A second level measures in an approximate but fast way the tilt-angle of the track. This can be used to trigger a third stage in which all hits associated to the track are processed locally to give a le ast-squares-fit to the track. The chip can then send out just the fitted t rack parameters instead of the individual electron coordinates. \n\nThis s elf-triggering capability could have a major application in the level-1 tr ack trigger proposed for the ATLAS upgrade for the sLHC. I will briefly su mmarise the track trigger requirements for the ATLAS Upgrade and highlight the advantages of a gaseous detector for this application\, followed by d iscussing one approach to the local intelligence needed to realise such a trigger.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=10&sess ionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=10&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Development of high performance tracking layers as a sandwich of o ptimised CMOS pixel sensors DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-39@cern.ch DESCRIPTION:Speakers: BAUDOT\, Jerome (Institut Pluridisciplinaire Hubert Curien (FR))\nWe propose to enhance the performances of tracking layers b y building a sandwich of low power time-integrating CMOS pixel sensors. Se nsors equipping one side of the layer offer a high spatial resolution (few μm)\, while the sensors on the other side focus on the time resolution ( few μs). The whole device targets a material budget lower than 0.5 % of X 0.\nWe will present the in-beam test results of a double-sided ladder feat uring 8 millions of pixels (18.4 × 18.4 μm2) read-out in 110 μs and an equivalent thickness of 0.6 % of X0\, build by the PLUME collaboration. Pl ans to reach 0.3 % of X0 will also be discussed.\nWe will then review the development of CMOS pixel sensors with various optimisations with respect to the spatial or time resolution. Especially the road to reach a few micr oseconds read-out time\, while maintaining the power budget at the few μW per pixel level will be described.\nThe conclusion will show possible imp lementation of these double-sided tracking layers.\n\nhttp://indico.cern.c h/contributionDisplay.py?contribId=39&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=39&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:The First Prototype for the FastTracker Processing Unit DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-12@cern.ch DESCRIPTION:Speakers: MAGALOTTI\, Daniel (Universita e INFN (IT))\nModern experiments search for extremely rare processes hidden in much larger back ground levels. As the experiment complexity and the accelerator background s and luminosity increase we need increasingly complex and exclusive selec tions. We present the first prototype of a new Processing Unit\, the core of the FastTracker processor for Atlas\, whose computing power is such tha t a couple of hundreds of them will be able to reconstruct all the track s with transverse momentum above 1 GeV in the ATLAS events up to Phase II instantaneous luminosities (5×1034 cm-2 s-1) with an event input rate of 100 kHz and a latency below hundreds of microseconds. We plan extremely po werful\, very compact and low consumption units for the far future\, essen tial to increase efficiency and purity of the Level 2 selected samples thr ough the intensive use of tracking.\nThis strategy requires massive comput ing power to minimize the online execution time of complex tracking algori thms. The time consuming pattern recognition problem\, generally referred to as the “combinatorial challenge”\, is beat by the Associative Memor y (AM) technology [2] exploiting parallelism to the maximum level: it comp ares the event to pre-calculated “expectations” or “patterns” (pat tern matching) at once looking for candidate tracks called “roads”. Th is approach reduces to linear the typical exponential complexity of the CP U based algorithms. The problem is solved by the time data are loaded into the AM devices. \nWe describe the board prototypes that face the very ch allenging aspects of the Processing Unit: a huge amount of detector cluste rs (“hits”) must be distributed at high rate with very large fan-out to all patterns (10 Millions of patterns will be located on 128 chips plac ed on a single board) and a huge amount of roads must be collected and sen t back to the FTK post-pattern-recognition functions. The Processing Unit consists of a 9U VME board\, the AMBoard\, controlled by an AUX card on th e back of the crate. The AMBoard has a modular structure consisting of 4 m ezzanines\, the Local Associative Memory Banks (LAMB). Each LAMB contains 32 Associative Memory (AM) chips\, 16 per side. The proto - AUX card provi des hits on 8 buses for a total of 12 Gbits/sec to the AMBoard through 12 high frequency serial links and will sink the found roads trough other 16 high frequency serial links (24 Gbits/sec). A special P3 connector allows the communication between the front and rear boards placed on the same VME slot. A custom board profile has been studied and simulated at the CAD t o guarantee a perfect board-to-board closure of the P3 connector without a backplane support in that region. A network of high speed serial links c haracterize the bus distribution on the AMBoard. The hit buses are fed to the four LAMBs and distributed to the 32 AM chips on the LAMB\, through fa nout chips. The LAMB realization has represented a significant technologic al challenge\, due to the high density of chips allocated on both sides\, and to the use of advanced packages and high frequency serial links.\n\nht tp://indico.cern.ch/contributionDisplay.py?contribId=12&sessionId=6&confId =154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=12&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Radiation-Hard and High-Speed Parallel Optical Engine DTSTART;VALUE=DATE-TIME:20120504T150000Z DTEND;VALUE=DATE-TIME:20120504T153000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-59@cern.ch DESCRIPTION:Speakers: Prof. GAN\, KK (Ohio State University)\nParallel opt ical engine allows a compact design for high-speed data transmission. The design is enabled by the readily available high-speed VCSEL arrays. With t he use of a 12-channel array operating at 10 Gb/s per channel\, a parallel optical engine can deliver an aggregated bandwidth of 120 Gb/s. With the spacing of 250 mm between two VCSELs\, the width of a VCSEL array is only 3 mm. This allows the fabrication of rather compact parallel optical engin e for installation at a location where space is at a premium. We have desi gned an ASIC for use in a parallel optical engine for a new layer of the A TLAS pixel detector for the initial phase of the LHC luminosity upgrade. T he ASIC is a 12-channel driver of a VCSEL array for operation up to 5 Gb/s . The ASIC is designed using a 130 nm CMOS process to enhance the radiatio n-hardness. A redundancy scheme has also been implemented to allow the byp ass of a broken VCSEL. We have received the ASIC and the performance up to 5 Gb/s is satisfactory. We are able to program the ASIC to bypass a broke n VCSEL. The power-on reset circuit is also successfully implemented which sets the ASIC to a default configuration with no signal steering. In addi tion\, we are able to set the drive current in individual channels. We pla n to port the design to the 130 nm SiGe BiCMOS process in order to operate at 10 Gb/s for an aggregated bandwidth of 120 Gb/s and some preliminary r esults of the design will be presented.\n\nhttp://indico.cern.ch/contribut ionDisplay.py?contribId=59&sessionId=5&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=59&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Dedicated Electronics-Based Pixel Tracking System for CMS for HL -LHC Luminosities DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-22@cern.ch DESCRIPTION:Speakers: GILMORE\, Jason (Texas A & M University (US))\nAddre ssing challenges of triggering in the High Luminosity LHC environment requ ire development of fast and efficient track-based triggering methods. We c onsider a dedicated electronics-based system\, which could be used as a co -processor performing fast tracking using data from the pixel detector for events passing the CMS Level-1 trigger. In this scenario\, a list of trac ks above a certain threshold will be made available for use at the very ea rly stages of the software-based CMS High Level trigger allowing fast and efficient reduction in the rate of events necessary to allow performing mo re complex and time-consuming reconstruction methods on surviving events. While primarily targeted for later stages of “Phase I” upgrades\, the same system can be utilized in the Phase II luminosity regime as part of t he Level-1 trigger logic. In this case\, the system will take advantage of the increased Level-1 trigger latency to perform tracking in regions of i nterest identified by the Level-1 calorimeter or muon triggers. In this sc enario\, the system will either confirm or deny presence of an energetic t rack and relay that information back to the Level-1 trigger decision logic before the final Level-1 decision to accept or reject an event is made.\n \nhttp://indico.cern.ch/contributionDisplay.py?contribId=22&sessionId=6&co nfId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=22&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Quadruple well CMOS MAPS for particle tracking with pixel-level an alog processing\, discrimination and time stamping DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-17@cern.ch DESCRIPTION:Speakers: Dr. ZUCCA\, Stefano (University of Pavia and INFN)\n In the last decade\, the use of standard deep submicron CMOS technologies for the implementation of monolithic active pixel sensors for HEP experime nts has been thoroughly investigated. One of the main issues with this app roach is the fact that the charge collection efficiency may be negatively affected by the presence of competitive N-wells used to integrate PMOS tra nsistors in the readout chain. These N-wells act as parasitics collecting electrodes subtracting part of the charge generated by a minimum ionizing particle (MIP) from the sensor. On the other hand\, PMOS transistors are n eeded to design high performance\, low power analog and digital blocks.\nA novel approach for isolating the PMOS competitive N-wells is based on the use of a planar 180 nm CMOS process with quadruple well called INMAPS. By means of an additional processing step\, an high energy deep P-well impla nt is deposited beneath the N-wells (except for the N-well diodes acting a s collecting electrodes). This implant creates a barrier for the charge di ffusing in the epitaxial layer\, preventing it from being collected by the positively biased N-wells of the in-pixel circuits and allowing a theoret ical charge collection efficiency of 100%. The NMOS transistors are design ed in heavily doped P-wells located over a lightly P-doped epitaxial layer about 10 μm thick\, which has been grown upon a relatively low resistivi ty substrate. The epitaxial layer\, featuring a higher resistivity than bo th the deep P-well and the substrate\, also plays an important role in the improvement of the charge collection properties: in fact\, the presence o f two small potential barriers (deep P-well/epitaxial layer or P-well/epit axial layer and epitaxial layer/substrate) keeps the carriers within the e pitaxial layer\, preventing them from diffusing through the substrate. The foundry provides two different typologies of epitaxial layer: standard re sistivity (about 50 Ω∙cm) and high resistivity (1 kΩ∙cm). Two lots o f chips called Apsel4well differing for the resistivity of the epitaxial l ayer\, have been fabricated (and delivered at the beginning of 2012). Comp aring the charge collection efficiency of the two different approaches wil l be possible to further investigate the role played by the epitaxial laye r resistivity on this performance.\nThe Apsel4well pixel features a 50 μm pitch\, complying with the requirements of the SVT Layer0 of the SuperB e xperiment. The collecting electrode consists of 4 interconnected N-well sq uare diodes each with a 1.5 μm side. The sensor is read out by a classica l channel for capacitive detectors including a charge preamplifier\, a sha per and a threshold discriminator\, followed by the in-pixel readout logic . Other than analog smaller (3x3) pixel matrices and single channels\, the Apsel4well chip also includes a 32x32 matrix which implements a sparsifie d readout architecture with time stamping in order to deal with the large amount of data expected in the experiments at the high luminosity collider s.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=17&sessionId= 6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=17&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Active Pixel Sensors in high-voltage CMOS technologies for ATLAS DTSTART;VALUE=DATE-TIME:20120503T153000Z DTEND;VALUE=DATE-TIME:20120503T160000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-16@cern.ch DESCRIPTION:Speakers: Dr. PERIC\, Ivan (Ruprecht-Karls-Universitaet Heidel berg (DE))\nActive pixel sensors in high-voltage CMOS technologies combine the possibility to equip the sensor segments with complex electronics and a drift-based signal collection. High radiation tolerance has been demons trated\, which makes the technology interesting for LHC applications. \nWe have designed a small pixel sensor demonstrator that can be readout using existing pixel or strip-readout systems. In this way\, we replace the pre sently used diode-based sensors with "intelligent" pixel sensors\, which s hould improve the characteristics of the detector. Smaller pixel size\, cl ustering\, or simultaneous readout of two sensor layers\, are theoreticall y possible.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=16&s essionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=16&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Fast Hardware Tracker for the ATLAS Trigger System DTSTART;VALUE=DATE-TIME:20120503T073000Z DTEND;VALUE=DATE-TIME:20120503T080000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-19@cern.ch DESCRIPTION:Speakers: Dr. PENNING\, Bjorn (University of Chicago (US))\nSe lecting interesting events with triggering is very challenging at the LHC due to the busy hadronic environment. Starting in 2014 the LHC will run wi th an energy of 14TeV and instantaneous luminosities which could exceed 10 ^34 interactions per cm^2 per second. The triggering in the ATLAS detector is realized using a three level trigger approach\, in which the first lev el (L1) is hardware based and the second (L2) and third (EF) stage are rea lized using large computing farms. \n\nIt is a crucial and non-trivial tas k for triggering to maintain a high efficiency for events of interest whil e suppressing effectively the very high rates of inclusive QCD processes\, which constitute mainly background. At the same time the trigger system h as to be robust and provide sufficient operational margins to adapt to cha nges in the running environment. In the current design\, track reconstruct ion can be performed only in limited regions of interest at L2 and the CPU requirements may limit this even further at the highest instantaneous lum inosities.\n\nProviding high quality track reconstruction over the entire detector volume for the L2 trigger decision would allow gains in efficienc y and background rejection for triggers on tau leptons\, b-hadrons and hel p reduce the luminosity dependence of isolation requirements for electrons and muons. The Fast Track Trigger (FTK) is an ongoing upgrade project aim ed at providing track reconstruction over the |eta|\n\nhttp://indico.cern. ch/contributionDisplay.py?contribId=19&sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=19&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Online tracking applications of the general purpose EDRO Board DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-32@cern.ch DESCRIPTION:Speakers: Prof. VILLA\, Mauro (Universita di Bologna e INFN (I T))\nThe capability to perform extremely fast track reconstruction online is becoming more and more important for the LHC upgrade as well as the nex t generation of HEP experiments\, where the expected instantaneous luminos ities (in excess of 10^34 /cm^2/s) and the very low signal/background rati o ask for fast and clean identification of the main characteristics of int eresting events.\nThe Slim5 R&D project studied different aspects of fast and high-precision tracking in dedicated hardware: data-push silicon senso rs\, high bandwidth DAQ systems and Associative Memories (AM) for fast tra ck identification. The central element of the development system is a high traffic board\, called EDRO\, capable of collecting and processing digita l data with an input rate of 16 Gbps. The input hits\, suitably formatted or clusterized\, are sent to an AM board sending back candidate tracks\, w hich are identified at a rate of 40 MHz. The EDRO board is then able to de liver triggers and formatted events for further processing. The EDRO-AM sy stem was first exploited on beam tests where it was able to process events at a maximum rate of 2.5 MHz\, trigger events with identified tracks (max imum latency 1 us) and provide a clean sample of events with well reconstr ucted tracks.\nThe flexibility of the EDRO-board design allows it to be co upled with completely different hit sources. In the ATLAS project called " FTK Vertical Slice" the EDRO board receives level 1 triggered data from a part of the inner detector and\, together with an AM board\, identifies tr acks for a possible use by the second level trigger processors.\nDesign cr iteria of the EDRO board as well as the systems in which it has been or wi ll be used are described together with the performance measured both in la b and real experiments with beam.\n\nhttp://indico.cern.ch/contributionDis play.py?contribId=32&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=32&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:The new variable resolution Associative Memory for Fast Track find ing DTSTART;VALUE=DATE-TIME:20120505T080000Z DTEND;VALUE=DATE-TIME:20120505T083000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-31@cern.ch DESCRIPTION:Speakers: ANNOVI\, Alberto (Istituto Nazionale Fisica Nucleare (IT))\nWe describe a VLSI processor for pattern recognition based on Cont ent Addressable Memory (CAM) architecture\,\noptimized for on-line track f inding in high-energy physics experiments.\nWe have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic.\nThe customized design maximizes the pattern density\, min imizes the power consumption and implements the\nfunctionalities needed fo r the planned Fast Tracker\, an ATLAS trigger upgrade project at LHC.\nWe introduce a new variable resolution pattern matching technique using “do n’t care” bits to set the pattern-matching\nwindow for each pattern an d each layer can be independently.\n\nhttp://indico.cern.ch/contributionDi splay.py?contribId=31&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=31&sessionId=3& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:CBC2: a microstrip readout ASIC with coincidence logic for trigger primitives at HL-LHC DTSTART;VALUE=DATE-TIME:20120504T123000Z DTEND;VALUE=DATE-TIME:20120504T130000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-30@cern.ch DESCRIPTION:Speakers: BRAGA\, Davide (STFC - Science & Technology Faciliti es Council (GB))\nWe present the design of a new version of the CBC (CMS B inary Chip) ASIC for the readout of CMS Tracker Phase-two upgrade. CBC2\, designed in 130nm CMOS\, doubles the input channels to 254 and will be bum p-bonded to the substrate. The ASIC is designed to instrument double layer modules in the outer tracker\, consisting of two overlaid silicon sensors with aligned microstrips\, and incorporates the logic to identify L1 trig ger primitives in the form of “stubs”: high transverse-momentum candid ates which are isolated from the low momentum background by selecting corr elated hits between two closely separated microstrip sensors. The function ality of the coincidence logic\, which includes rejection of wide clusters and offset correction to account for the position of the module in the R- Φ plane\, is described in detail.\n\nhttp://indico.cern.ch/contributionDi splay.py?contribId=30&sessionId=5&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=30&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:The CBC microstrip readout chip for LHC phase II DTSTART;VALUE=DATE-TIME:20120504T093000Z DTEND;VALUE=DATE-TIME:20120504T100000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-37@cern.ch DESCRIPTION:Speakers: PESARESI\, Mark (Imperial College Sci.\, Tech. & Med . (GB))\nThe CBC is a 130 nm CMOS chip designed for the readout of short s ilicon microstrips for the CMS Phase II tracker upgrade. It is a 128 chann el wire-bonded chip which can be DC coupled to sensors of either polarity. The replacement tracker is also expected to provide limited tracking info rmation to the Level 1 hardware trigger. With a binary front end the chip is well suited to adapting for use in stacked strip sensor modules in orde r to promptly identify high transverse momentum candidates. In this versio n\, binary data are retained in a 256 deep pipeline and transmitted in an unsparsified format in response to an incoming trigger. The CBC performanc e has been evaluated in the laboratory and in a test beam. Details of the design and latest results of the measured performance will be presented.\n \nhttp://indico.cern.ch/contributionDisplay.py?contribId=37&sessionId=5&co nfId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=37&sessionId=5& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A 0.18 μm CMOS Low-Power Radiation Sensor for Asynchronous Event -Driven UWB Wireless Transmission DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-36@cern.ch DESCRIPTION:Speakers: Dr. GABRIELLI\, Alessandro (Universita e INFN (IT))\ nWe describe the design of a floating gate-based MOS sensor embedded in a read-out CMOS sensing element used as a radiation sensor. The read-out cel l asynchronously triggers an all-digital Ultra-Wide Band (UWB) transmitter operating in a 0-5GHz band\, with a repetition frequency\, which dynamica lly depends on the radiation level. The trigger signal ranges 20 to 30MHz\ , with a designed sensor input range\, between 0 and 2V. \n The floating g ate MOS sensor has been recently characterized and here emulated with a co mmercial radiation-sensitive FETs based on a metal-oxide-silicon p-channel structure\, for a 2V variation given an equivalent absorbed dose of 100ra d within 1 and 100krad. A maximum sensitivity of 1mV/rad is estimated up t o 10krad. The paper shows the design of a preliminary microelectronic circ uit that includes a sensor\, an oscillator and modulator\, which is now un der submission. The prototype will be interfaced to an external power supp ly and to an antenna for pulse transmission\, to provide a preliminary pro of-of-concept validation before a complete integration. Given the small es timated area of the complete chip prototype\, comprising the antenna\, i.e . less than 1mm2\, the IC can enable a large variety of applications for s pot radiation monitoring systems (High-Energy Physics experiments might be nefit of this concept). The paper shows measurements on a mini test-board equipped with the full-custom components comprising an external transmitte r IC that will be integrated in the ASIC prototype (TowerJazz). First meas urements\, obtained at the “Istituto Italiano di Tecnologia”\, Center for Space Human Robotics\, demonstrate the feasibility of the proposed eve nt-driven asynchronous Ultra-Low Power (ULP) UWB transmission. The Science and Technology Facility Council of the Rutherford Appleton Laboratory (RA L)\, UK\, supports the entire research.\n\nhttp://indico.cern.ch/contribut ionDisplay.py?contribId=36&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=36&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Study of system integration for the pixel detector of the PANDA ex periment DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-35@cern.ch DESCRIPTION:Speakers: CALVO\, Daniela (INFN-Torino (IT))\nThe PANDA experi ment will make use of antiproton cooled beams of unprecedented quality\, t hat will become available at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt\, featuring up to 2•10^11 antiprotons and momentum b etween 1.5 – 15 GeV/c.\nTo handle forward particle distribution due to t he Lorentz boost\, the apparatus is arranged in an asymmetric layout aroun d the interaction point between antiprotons and pellet or gas jet target. \nThis peculiarity requires a tracking detector with a forward design and in particular an innermost Micro Vertex Detector (MVD) based on silicon de vices with an innovative design in an unusual geometry. The material budge t of this silicon tracker has to be minimized in view of particle momenta ranging from few hundreds of MeV/c up to several GeV/c. Besides high inter action rate asks for fast data readout being PANDA without low-level trigg er selection and particle identification is planned over the full range of energies.\nTo cope with these requirements MVD includes innermost layers made of thinned epitaxial silicon hybrid pixel detectors and outermost com posed of double side silicon micro strips.\nIn particular the mechanics in tegration of the pixel detector is a challenge due to the compact volume o f the MVD asking for specific solutions as carbon foam both to increase th e heat dissipation towards the cooling pipes and acting as mechanics suppo rts.\nTo cope with high data rate new non-triggered readout chips develope d in 130 nm CMOS technology feature high speed readout and charge measurem ent with Time over Threshold\, and to deal with the limited material budge t request new aluminium strips are developed for data transmission and spe cific busses design are under study. \nResults concerning the developments of prototypes to solve critical items will be presented.\n\nhttp://indico .cern.ch/contributionDisplay.py?contribId=35&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=35&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:A Fast General-Purpose Clustering Algorithm Based on FPGAs for Hig h-Throughput Data Processing DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-34@cern.ch DESCRIPTION:Speakers: BERETTA\, Matteo Mario (Istituto Nazionale Fisica Nu cleare (IT))\nWe present a fast general-purpose algorithm for high-through put clustering of data ”with a two dimensional organization”. The\nalg orithm is designed to be implemented with FPGAs or custom electronics. The key feature is a processing time that scales\nlinearly with the amount of data to be processed. This means that clustering can be performed in pipe line with the readout\, without\nsuffering from combinatorial delays due t o looping multiple times through all the data. This feature makes this alg orithm especially\nwell suited for problems where the data has high densit y\, e.g. in the case of tracking devices working under high-luminosity\nco ndition such as those of LHC or Super-LHC.\nThe algorithm is organized in two steps: the first step (core) clusters the data\; the second step analy zes each cluster of data to\nextract the desired information. The current algorithm is developed as a clustering device for modern high-energy physi cs pixel\ndetectors. However\, the algorithm has much broader field of app lications. In fact\, its core does not specifically rely on the kind of\nd ata or detector it is working for\, while the second step can and should b e tailored for a given application. For example\, in case of\nspatial meas urement with silicon pixel detectors\, the second step performs center of charge calculation. Applications can thus be\nforeseen to other detectors and other scientific fields ranging from HEP calorimeters to medical imagi ng.\nAn additional advantage of this two steps approach is that the typica l clustering related calculations (second step) are separated\nfrom the co mbinatorial complications of clustering. This separation simplifies the de sign of the second step and it enables it to\nperform sophisticated calcul ations achieving offline-quality in online applications. The algorithm is general purpose in the sense\nthat only minimal assumptions on the kind of clustering to be performed are made.\n\nhttp://indico.cern.ch/contributio nDisplay.py?contribId=34&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=34&sessionId=6& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Trigger and Data Acquisition Strategy for the LHCb Upgrade DTSTART;VALUE=DATE-TIME:20120503T083000Z DTEND;VALUE=DATE-TIME:20120503T090000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-54@cern.ch DESCRIPTION:Speakers: ARTUSO\, Marina (Syracuse University (US))\, ARTUSO\ , marina (syracuse university)\, ARTUSO\, Marina (Department of Physics)\n The LHCb experiment is making strong strides towards the exploitation of p hysics opportunities that may lead to the discovery and elucidation of phy sics beyond the Standard Model. While LHCb will be able to measure many i nteresting channels in the upcoming few years\, an upgrade aimed at incre asing its sensitivity by about a factor of 10 will broaden the discovery p otential of the experiment. Two key elements of the upgrade are the abili ty of reading out the detector at 40 MHz and a flexible and efficient soft ware trigger\, that exploits the unique features of the signal events soug ht. The key elements of the data acquisition and trigger strategies will b e discussed\, with particular emphasis on how the tracking information is incorporated to provide an effective selection of interesting beauty and c harm events.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=54& sessionId=1&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=54&sessionId=1& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Pattern recognition with vector-type detector hits DTSTART;VALUE=DATE-TIME:20120505T093000Z DTEND;VALUE=DATE-TIME:20120505T100000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-57@cern.ch DESCRIPTION:Speakers: Dr. FRÜHWIRTH\, Rudolf (ÖAW\, HEPHY Vienna)\nNovel types of "intelligent" trackers provide hits consisting of position-cum-d irection rather than position alone. \nWe study several types of track fin ding algorithms in this context\, for example the Hough transform\, neural networks\, a cellular automaton\, track following\, and the combinatorial Kalman filter. The performance of the algorithms is compared on simulated data in a simplified detector model\, for various assumptions about the o ccupancy. We also voice some conjectures on which algorithms might be prom ising candidates for online deployment.\n\nhttp://indico.cern.ch/contribut ionDisplay.py?contribId=57&sessionId=3&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=57&sessionId=3& confId=154525 END:VEVENT BEGIN:VEVENT SUMMARY:Progress on silicon and carbon foam composite wafers for interpose r or hybrid use DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130520T011317Z UID:indico-contribution-154525-50@cern.ch DESCRIPTION:Speakers: GARCIA-SCIVERES\, Mauricio (Lawrence Berkeley Nation al Lab. (US))\nWe present updated results of prototyping silicon and carbo n foam composite wafers for use as either low mass interposers or active h ybrids. Composite 4 inch wafers have been prototyped with approximately 4 mm thickness and average density 20% that of silicon. A composite wafer co nsists of top and bottom silicon face-plates on a carbon foam core\, assem bled with adhesive that can withstand 300 C process temperature. Embedded in the foam core are vertical silicon “fins” that can have passive ver tical metal traces for interposer applications or active IC's for hybrid a pplications. Metal contacts on the vertical fins are exposed by grinding t he face-plates. Lithographic processing of the composite wafer can then be applied to interconnect the exposed contacts. This final step has not yet been prototyped.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribI d=50&sessionId=6&confId=154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=50&sessionId=6& confId=154525 END:VEVENT END:VCALENDAR