CSC Upgrade electronics technical discussion

17 Dec 2009, 09:00 → 18 Dec 2009, 18:00 Europe/Zurich

1/1-025 (CERN)

Paul Padley (Rice University)

Technical engineering discussion of CSC upgrade electronics

Thursday 17 December

09:00 → 11:00 DCFEB discussion

Overview of design and Short presentations what options will and will not be on the DCFEB prototype.

document DCFEB2TMB_opt.pdf DCFEB2TMB_opt.xlsx

slides DCFEB_Upgrade_WrkShp_Rice_17_Dec_2009.pdf DCFEB_Upgrade_WrkShp_Rice_17_Dec_2009.pptx

11:00 → 12:00 DCFEB to TMB data interface

DCFEB to TMB data interface,

a) options with pros and cons
b) comparator clock path and phase control
Ben will write up a document listing the options that have been

proposed so far,
And start a list of pros and cons for each option.
This can be a starting point for discussion.

slides TMB_skewclear_option.pdf.pdf

11:00 → 12:00 TMB Overview

Overview of design and plan, and plans to test 48-bit channel Links.

slides TMB_Upgrades.pdf TMB_Upgrades.ppt

14:00 → 16:00 Port Card, Muon Sorter and optical links

slides MPC_121709.pdf

16:00 → 17:00 Tracker links

A description of what is being discussed in the tracker world, to allow some cross fertilization

slides TKOpticalLinks-1.pdf

Friday 18 December

11:00 → 12:00 CFEB-TMB communication follow up discussion

After meetings Thursday much work was done on this. We should discuss

13:00 → 15:00 Trackfinder

slides Rice-workshop-2009-12-18.pdf Rice-workshop-2009-12-18.pptx

slides upgradeWorkshop-Rice-Dec-2009.pdf

15:00 → 16:00 Components issues

Discussion of component issues:
(For the purpose of soliciting feedback/opinions/knowledge from other
engineers
concerning design issues on the DCFEB)
a)QPLL, availability, procurement, compatibility with sLCH future
plans.
b)FPGA family issues, cost, lower voltages, higher current.
c)Voltage regulators for <1.2V, rad testing...
d)Protection from LVDB? Power distribution...

slides FPGA.pdf

16:00 → 17:00 Division of responsibilities

Discussion on division of labor/responsibility particularly at/between board boundaries: a) LVDB, cables, fiber optics, patch panel, backplane? ...

17:00 → 18:00 radiation testing