BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CERN//INDICO//EN BEGIN:VEVENT SUMMARY:The First Prototype for the FastTracker Processing Unit DTSTART;VALUE=DATE-TIME:20120503T180000Z DTEND;VALUE=DATE-TIME:20120503T190000Z DTSTAMP;VALUE=DATE-TIME:20130526T025735Z UID:indico-contribution-12@cern.ch DESCRIPTION:Speakers: MAGALOTTI\, Daniel (Universita e INFN (IT))\nModern experiments search for extremely rare processes hidden in much larger back ground levels. As the experiment complexity and the accelerator background s and luminosity increase we need increasingly complex and exclusive selec tions. We present the first prototype of a new Processing Unit\, the core of the FastTracker processor for Atlas\, whose computing power is such tha t a couple of hundreds of them will be able to reconstruct all the track s with transverse momentum above 1 GeV in the ATLAS events up to Phase II instantaneous luminosities (5×1034 cm-2 s-1) with an event input rate of 100 kHz and a latency below hundreds of microseconds. We plan extremely po werful\, very compact and low consumption units for the far future\, essen tial to increase efficiency and purity of the Level 2 selected samples thr ough the intensive use of tracking.\nThis strategy requires massive comput ing power to minimize the online execution time of complex tracking algori thms. The time consuming pattern recognition problem\, generally referred to as the “combinatorial challenge”\, is beat by the Associative Memor y (AM) technology [2] exploiting parallelism to the maximum level: it comp ares the event to pre-calculated “expectations” or “patterns” (pat tern matching) at once looking for candidate tracks called “roads”. Th is approach reduces to linear the typical exponential complexity of the CP U based algorithms. The problem is solved by the time data are loaded into the AM devices. \nWe describe the board prototypes that face the very ch allenging aspects of the Processing Unit: a huge amount of detector cluste rs (“hits”) must be distributed at high rate with very large fan-out to all patterns (10 Millions of patterns will be located on 128 chips plac ed on a single board) and a huge amount of roads must be collected and sen t back to the FTK post-pattern-recognition functions. The Processing Unit consists of a 9U VME board\, the AMBoard\, controlled by an AUX card on th e back of the crate. The AMBoard has a modular structure consisting of 4 m ezzanines\, the Local Associative Memory Banks (LAMB). Each LAMB contains 32 Associative Memory (AM) chips\, 16 per side. The proto - AUX card provi des hits on 8 buses for a total of 12 Gbits/sec to the AMBoard through 12 high frequency serial links and will sink the found roads trough other 16 high frequency serial links (24 Gbits/sec). A special P3 connector allows the communication between the front and rear boards placed on the same VME slot. A custom board profile has been studied and simulated at the CAD t o guarantee a perfect board-to-board closure of the P3 connector without a backplane support in that region. A network of high speed serial links c haracterize the bus distribution on the AMBoard. The hit buses are fed to the four LAMBs and distributed to the 32 AM chips on the LAMB\, through fa nout chips. The LAMB realization has represented a significant technologic al challenge\, due to the high density of chips allocated on both sides\, and to the use of advanced packages and high frequency serial links.\n\nht tp://indico.cern.ch/contributionDisplay.py?contribId=12&sessionId=6&confId =154525 LOCATION:INFN Pisa URL:http://indico.cern.ch/contributionDisplay.py?contribId=12&sessionId=6& confId=154525 END:VEVENT END:VCALENDAR