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SUMMARY:Quadruple well CMOS MAPS for particle tracking with pixel-level an
 alog processing\, discrimination and time stamping
DTSTART;VALUE=DATE-TIME:20120503T180000Z
DTEND;VALUE=DATE-TIME:20120503T190000Z
DTSTAMP;VALUE=DATE-TIME:20130526T071927Z
UID:indico-contribution-17@cern.ch
DESCRIPTION:Speakers: Dr. ZUCCA\, Stefano (University of Pavia and INFN)\n
 In the last decade\, the use of standard deep submicron CMOS technologies 
 for the implementation of monolithic active pixel sensors for HEP experime
 nts has been thoroughly investigated. One of the main issues with this app
 roach is the fact that the charge collection efficiency may be negatively 
 affected by the presence of competitive N-wells used to integrate PMOS tra
 nsistors in the readout chain. These N-wells act as parasitics collecting 
 electrodes subtracting part of the charge generated by a minimum ionizing 
 particle (MIP) from the sensor. On the other hand\, PMOS transistors are n
 eeded to design high performance\, low power analog and digital blocks.\nA
  novel approach for isolating the PMOS competitive N-wells is based on the
  use of a planar 180 nm CMOS process with quadruple well called INMAPS. By
  means of an additional processing step\, an high energy deep P-well impla
 nt is deposited beneath the N-wells (except for the N-well diodes acting a
 s collecting electrodes). This implant creates a barrier for the charge di
 ffusing in the epitaxial layer\, preventing it from being collected by the
  positively biased N-wells of the in-pixel circuits and allowing a theoret
 ical charge collection efficiency of 100%. The NMOS transistors are design
 ed in heavily doped P-wells located over a lightly P-doped epitaxial layer
  about 10 μm thick\, which has been grown upon a relatively low resistivi
 ty substrate. The epitaxial layer\, featuring a higher resistivity than bo
 th the deep P-well and the substrate\, also plays an important role in the
  improvement of the charge collection properties: in fact\, the presence o
 f two small potential barriers (deep P-well/epitaxial layer or P-well/epit
 axial layer and epitaxial layer/substrate) keeps the carriers within the e
 pitaxial layer\, preventing them from diffusing through the substrate. The
  foundry provides two different typologies of epitaxial layer: standard re
 sistivity (about 50 Ω∙cm) and high resistivity (1 kΩ∙cm). Two lots o
 f chips called Apsel4well differing for the resistivity of the epitaxial l
 ayer\, have been fabricated (and delivered at the beginning of 2012). Comp
 aring the charge collection efficiency of the two different approaches wil
 l be possible to further investigate the role played by the epitaxial laye
 r resistivity on this performance.\nThe Apsel4well pixel features a 50 μm
  pitch\, complying with the requirements of the SVT Layer0 of the SuperB e
 xperiment. The collecting electrode consists of 4 interconnected N-well sq
 uare diodes each with a 1.5 μm side. The sensor is read out by a classica
 l channel for capacitive detectors including a charge preamplifier\, a sha
 per and a threshold discriminator\, followed by the in-pixel readout logic
 . Other than analog smaller (3x3) pixel matrices and single channels\, the
  Apsel4well chip also includes a 32x32 matrix which implements a sparsifie
 d readout architecture with time stamping in order to deal with the large 
 amount of data expected in the experiments at the high luminosity collider
 s.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=17&sessionId=
 6&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=17&sessionId=6&
 confId=154525
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