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SUMMARY:A fast digital readout architecture for vertically integrated pixe
 l sensors
DTSTART;VALUE=DATE-TIME:20120503T180000Z
DTEND;VALUE=DATE-TIME:20120503T190000Z
DTSTAMP;VALUE=DATE-TIME:20130524T034205Z
UID:indico-contribution-25@cern.ch
DESCRIPTION:Speakers: Dr. GIORGI\, Filippo Maria (Universita e INFN (IT))\
 nA digital architecture for fast sparsified readout has been developed for
  the implementation of wide 3D pixel sensors. The Italian VIPIX collaborat
 ion is realizing two prototypes exploiting the Tezzaron-Chartered vertical
  integration process in order to build a 12k-pixel 3D deep n-well MAPS sen
 sor\, and a 3D 4k-pixel front-end chip\, with 50 um pitch\, for a fully de
 pleted silicon sensor. In both cases the digital and analog circuits are i
 mplemented on dedicated tiers in order to reduce the digital noise inducti
 on and enhance the digital logic at pixel level. The dense in-pixel logic 
 allows for innovative sparsified hit extraction techniques\, in order to r
 educe the pixel occupancy. The readout logic we propose can face an input 
 hit rate of the order of 100MHz/cm2 and allows a time resolution of 100 ns
 \, in addition it can be configured to work in data-driven or triggered mo
 de. \nThe technology process is a Chartered CMOS 130 nm\, this feature siz
 e presents an intrinsic radiation tolerance and allow the use of foundry
 ’s standard cells. The architecture has been deeply investigated in term
 s of efficiency on a wide span of input parameters (hit rate\, time resolu
 tion\, trigger latency etc.) thanks to a parameterized VHDL synthesizable 
 model\, that has been designed to match even larger matrices of pixels. Th
 e model was stimulated within a complex test bench environment that includ
 ed a Monte Carlo generator for the hit extraction\, a simulation monitor a
 nd a C++ framework for the efficiency analysis and error detection. The fl
 exibility of the code allow to easily tailor the architecture and of the t
 est bench on different matrix dimensions: we observed this scalable archit
 ecture working properly even with bigger matrices\, of the order of 50k pi
 xels. \nThe paper presents the readout efficiency versus a variety of para
 meters as the clock rate\, the pixel hit-rate and\nthe time-stamp resoluti
 on. The overall project leads to design a high-density thin vertex detecto
 r with an on-chip\nsparsified digital readout system\, for particle tracki
 ng\, aimed at matching the requirements of future high-energy physics\nexp
 eriments like SuperB.\n\nhttp://indico.cern.ch/contributionDisplay.py?cont
 ribId=25&sessionId=6&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=25&sessionId=6&
 confId=154525
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