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SUMMARY:General purpose\, high-performance and energy-efficient x86 based 
 computing with Many-Core Technologies (TFLOPS on a chip)
DTSTART;VALUE=DATE-TIME:20120503T090000Z
DTEND;VALUE=DATE-TIME:20120503T094500Z
DTSTAMP;VALUE=DATE-TIME:20130525T055222Z
UID:indico-contribution-27@cern.ch
DESCRIPTION:Speakers: CORNELIUS\, Herbert ()\nAs we see Moore's Law alive 
 and well\, more and more parallelism is introduced to all computing platfo
 rms on all levels of integration and programming to achieve higher perform
 ance and energy efficiency. We will discuss the new Intel(r) Many Integrat
 ed Core (MIC) architecture for highly-parallel workloads with general purp
 ose\, energy efficient TFLOPS performance on a single chip. We will also d
 iscuss the journey to ExaScale including technology trends for high-perfor
 mance and look at some of the R&D areas for HPC at Intel.\n\nhttp://indico
 .cern.ch/contributionDisplay.py?contribId=27&confId=159120
LOCATION:Intel\, Germany
URL:http://indico.cern.ch/contributionDisplay.py?contribId=27&confId=15912
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