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SUMMARY:Development of high performance tracking layers as a sandwich of o
 ptimised CMOS pixel sensors
DTSTART;VALUE=DATE-TIME:20120503T180000Z
DTEND;VALUE=DATE-TIME:20120503T190000Z
DTSTAMP;VALUE=DATE-TIME:20130620T042737Z
UID:indico-contribution-39@cern.ch
DESCRIPTION:Speakers: BAUDOT\, Jerome (Institut Pluridisciplinaire Hubert 
  Curien (FR))\nWe propose to enhance the performances of tracking layers b
 y building a sandwich of low power time-integrating CMOS pixel sensors. Se
 nsors equipping one side of the layer offer a high spatial resolution (few
  μm)\, while the sensors on the other side focus on the time resolution (
 few μs). The whole device targets a material budget lower than 0.5 % of X
 0.\nWe will present the in-beam test results of a double-sided ladder feat
 uring 8 millions of pixels (18.4 × 18.4 μm2) read-out in 110 μs and an 
 equivalent thickness of 0.6 % of X0\, build by the PLUME collaboration. Pl
 ans to reach 0.3 % of X0 will also be discussed.\nWe will then review the 
 development of CMOS pixel sensors with various optimisations with respect 
 to the spatial or time resolution. Especially the road to reach a few micr
 oseconds read-out time\, while maintaining the power budget at the few μW
  per pixel level will be described.\nThe conclusion will show possible imp
 lementation of these double-sided tracking layers.\n\nhttp://indico.cern.c
 h/contributionDisplay.py?contribId=39&sessionId=6&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=39&sessionId=6&
 confId=154525
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