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SUMMARY:Radiation tolerant IP-cores for the control and readout of Front-E
 nd electronics in future Silicon detectors
DTSTART;VALUE=DATE-TIME:20120503T180000Z
DTEND;VALUE=DATE-TIME:20120503T190000Z
DTSTAMP;VALUE=DATE-TIME:20130619T213756Z
UID:indico-contribution-45@cern.ch
DESCRIPTION:Speakers: MAGAZZU\, Guido (Univ. of California Santa Barbara (
 US))\nThe FF-LYNX protocol represents an innovative and flexible solution 
 for the distribution of Timing\, Trigger and Control (TTC) signals and the
  data readout in future detectors for the High Energy Physics. Transmitter
  (TX) and Receiver (RX) interfaces to serial electrical links implementing
  the FF-LYNX protocol with different speed options (160Mbps\, 320Mbps\, 64
 0Mbps) have been developed. They are available as VHDL cores for integrati
 on in commercial FPGA devices and as Standard-Cell based cores\, designed 
 and developed in the IBM CMOS 130nm technology. Architecture and behavior 
 of the interfaces and results of test and characterization of the prototyp
 es embedded in the test ASICs fabricated in 2011 will be presented. \n\nRa
 diation tolerant FIFOs have been developed as input and output buffers in 
 TX and RX interfaces. They are available as stand-alone IP-cores and can b
 e used in Front-End ASICs or other circuits where radiation tolerant data 
 buffers are required. Architecture and behavior of these FIFO blocks will 
 be described as well as results of irradiation tests performed on the thei
 r prototypes. \n  \nResults of tests performed with FF-LYNX Encoder and De
 coder directly coupled with the GBT Transmitter and Receiver in an FPGA pr
 oof-of-concept demonstrator of optical links handled by GBT transceivers a
 nd running data encoded with the FF-LYNX protocol will be presented as wel
 l as the architecture and the behavior of the Data Concentrator Module\, a
  VHDL core that merges input data transmitted from multiple sources throug
 h “low-speed” serial links into one (or more) “high-speed” output 
 serial links. \n\nFinally future plans\, mainly focused on the development
  of interfaces with improved speed and power performances and including cu
 stom Serializer and Deserializer modules will be presented.\n\nhttp://indi
 co.cern.ch/contributionDisplay.py?contribId=45&sessionId=6&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=45&sessionId=6&
 confId=154525
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