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SUMMARY:Asynchronous readout architectures for Tracker Front-End ASICs
DTSTART;VALUE=DATE-TIME:20120504T100000Z
DTEND;VALUE=DATE-TIME:20120504T103000Z
DTSTAMP;VALUE=DATE-TIME:20130526T015332Z
UID:indico-contribution-48@cern.ch
DESCRIPTION:Speakers: Dr. JOHNSON\, Marvin (Fermilab)\, JOHNSON\, Marvin (
 Fermi National Accelerator Lab. (US))\nWe preset a design of a front end A
 SIC that combines a level 1\ntrigger and normal event readout.  It uses as
 ynchronous logic through\nout the design to reduce both power consumption 
 and noise sensitivity.\nThe only clock used is the 40 MHz LHC clock.  A te
 st chip based on\nthis design is planned to be submitted in July of this y
 ear.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=48&sessionI
 d=5&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=48&sessionId=5&
 confId=154525
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