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SUMMARY:Radiation-Hard and High-Speed Parallel Optical Engine
DTSTART;VALUE=DATE-TIME:20120504T150000Z
DTEND;VALUE=DATE-TIME:20120504T153000Z
DTSTAMP;VALUE=DATE-TIME:20130620T101355Z
UID:indico-contribution-59@cern.ch
DESCRIPTION:Speakers: Prof. GAN\, KK (Ohio State University)\nParallel opt
 ical engine allows a compact design for high-speed data transmission. The 
 design is enabled by the readily available high-speed VCSEL arrays. With t
 he use of a 12-channel array operating at 10 Gb/s per channel\, a parallel
  optical engine can deliver an aggregated bandwidth of 120 Gb/s. With the 
 spacing of 250 mm between two VCSELs\, the width of a VCSEL array is only 
 3 mm. This allows the fabrication of rather compact parallel optical engin
 e for installation at a location where space is at a premium. We have desi
 gned an ASIC for use in a parallel optical engine for a new layer of the A
 TLAS pixel detector for the initial phase of the LHC luminosity upgrade. T
 he ASIC is a 12-channel driver of a VCSEL array for operation up to 5 Gb/s
 . The ASIC is designed using a 130 nm CMOS process to enhance the radiatio
 n-hardness. A redundancy scheme has also been implemented to allow the byp
 ass of a broken VCSEL. We have received the ASIC and the performance up to
  5 Gb/s is satisfactory. We are able to program the ASIC to bypass a broke
 n VCSEL. The power-on reset circuit is also successfully implemented which
  sets the ASIC to a default configuration with no signal steering. In addi
 tion\, we are able to set the drive current in individual channels. We pla
 n to port the design to the 130 nm SiGe BiCMOS process in order to operate
  at 10 Gb/s for an aggregated bandwidth of 120 Gb/s and some preliminary r
 esults of the design will be presented.\n\nhttp://indico.cern.ch/contribut
 ionDisplay.py?contribId=59&sessionId=5&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=59&sessionId=5&
 confId=154525
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