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SUMMARY:Instrumentation of a track trigger with double buffer front-end  a
 rchitecture
DTSTART;VALUE=DATE-TIME:20120503T100000Z
DTEND;VALUE=DATE-TIME:20120503T103000Z
DTSTAMP;VALUE=DATE-TIME:20130525T055315Z
UID:indico-contribution-7@cern.ch
DESCRIPTION:Speakers: WARDROPE\, David (University College London (UK))\nT
 he planned high luminosity upgrade for the LHC (SLHC)\, will increase  the
  collision rate in the ATLAS detector by approximately a factor 5  beyond 
 the present LHC design goal\, while also increasing the number of  pile-up
  collisions in each event by a similar factor. This means that \nthe level
 -1 trigger must achieve a higher rejection factor in a more  difficult env
 ironment. We describe a possible design which splits the  level-1 trigger 
 into a two-level system\, where the first level\, using only  calorimetry 
 and muon chambers\, defines regions of interest in the tracker \nfrom whic
 h to extract information for a second\, refined trigger. The use of a two-
 buffer front-end architecture will allow a  significantly longer decision 
 time to move data off the detector  keeping the data bandwidth and buffer 
 sizes moderate. We will describe  the implementation of the scheme in the 
 ATLAS tracker front-end  electronics and the simulated performance of the 
 system. Results on thresholds\, rejection\, bandwidth and trigger latency 
 will be shown and  compared with the present requirements for SLHC upgrade
  in ATLAS.\n\nhttp://indico.cern.ch/contributionDisplay.py?contribId=7&ses
 sionId=1&confId=154525
LOCATION:INFN Pisa
URL:http://indico.cern.ch/contributionDisplay.py?contribId=7&sessionId=1&c
 onfId=154525
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