154525 Conferences false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] Sezione di Pisa (IT) fabrizio.palla@cern.ch 15116 With the increasing capabilities of microelectronic technology, future particle detectors will be able to yield high level features that are not only simple geometrical positions or energy measurements in the sensors used. The ability to compute such high level primitives in near real-time is what we characterize as &ldquo;intelligence&rdquo;.<br /> This will enable the construction of detectors with novel functionalities, allowing the trigger logic or even the off-line analysis in experiments to handle immediately more complex features of the measurements. Two examples of new primitives are near real-time charged particle direction or charge clusters without pixel boundary effects. But the addition of such intelligence has practical challenges and in particular system issues must be addressed, such as material budget and power density.<br /> This Workshop would provide a discussion forum for the community of scientists and engineers working on development of intelligent devices.<br /> The objectives of the workshop will be to enhance the cross breeding of ideas, to compare concepts for incorporating intelligence in particle trackers, and to explore possibilities for application to other areas.<br /> The format of the workshop is on plenary sessions, for a duration of 2.5 days.<br /> This Workshop is the second of the series. The <a href="https://indico.cern.ch/conferenceDisplay.py?confId=68677" target="_blank"> first one </a>was held in Berkeley in 2010. <br /> Registration for the workshop will be <b>by invitation</b> following review of abstracts. <br /> The abstract submission deadline is <b>January 14, 2012</b>. <br /> Proceedings of the workshop will be published in <b>JINST</b>. <br /> Deadline extended to January 28, 2012. <br /> We invite submission of abstracts in the following subjects:<br /> *Applications of intelligent detectors<br /> *Coupled layer and monolithic architectures<br /> *Development of specific components<br /> *Electronic circuits (3D and conventional) on- and off-detector<br /> *High speed communication<br /> *System integration<br /> *Real time pattern recognition<br /> *Advanced Algorithms False INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-03T08:00:00 2012-05-05T18:00:00 2011-09-08T14:54:03 2012-07-19T06:36:21 Europe/Paris 40 false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] Universite d'Aix - Marseille II (FR) clemens@cppm.in2p3.fr Universite d'Aix - Marseille II (FR) clemens@cppm.in2p3.fr Universitaet Bonn (DE) marlon.barbero@cern.ch Lawrence Berkeley National Lab. (US) mgarcia-sciveres@lbl.gov Universite d'Aix - Marseille II (FR) patrick.pangaud@cern.ch Universite d'Aix - Marseille II (FR) alexandre.rozanov@cern.ch Universitat Bonn arutinov@physik.uni-bonn.de Rheinische-Friedrich-Wilhelms- Univ.-Univ. Bonn, Physikalisches hans.krueger@cern.ch stephanie.godiot@cern.ch Universitaet Bonn (DE) wermes@uni-bonn.de Universitaet Bonn (DE) hemperek@physik.uni-bonn.de LBNL amekkaoui@lbl.gov INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-04T08:30:00 2012-05-04T09:00:00 00:30 Even if 3D electronics suffers difficult beginnings, industrial trends are now strongly pushing that way to a production phase. Keeping in mind the usual arguments of power consumption, speed, technology mixing, new and less expected possibilities are now appearing. In trackers world, few attempts have been made to introduce 3D not only as an alternative to shrinking technologies but also as a source of new possibilities. Post-processed TSV have yet proven to be feasible in HEP circuits allowing for new routing schemes of circuits IO without modifying the original process. On the other hand, 3D structures as part as the chip process offers more possibilities but the price to pay is the poor commercial offers. With new ideas for building depleted sensors with standard MOS process, 3D tech could allow a fully integrated fabrication of future vertex chips (sensor + read-out) in the same production chain. This talk will try to give an idea of the efforts made and of the results obtained using these 3D techniques in the scope of HL LHC R&D programs (ATLAS) slides doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link paper doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link 2013-05-20 2013-05-21