154525 Conferences false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] Sezione di Pisa (IT) fabrizio.palla@cern.ch 15116 With the increasing capabilities of microelectronic technology, future particle detectors will be able to yield high level features that are not only simple geometrical positions or energy measurements in the sensors used. The ability to compute such high level primitives in near real-time is what we characterize as &ldquo;intelligence&rdquo;.<br /> This will enable the construction of detectors with novel functionalities, allowing the trigger logic or even the off-line analysis in experiments to handle immediately more complex features of the measurements. Two examples of new primitives are near real-time charged particle direction or charge clusters without pixel boundary effects. But the addition of such intelligence has practical challenges and in particular system issues must be addressed, such as material budget and power density.<br /> This Workshop would provide a discussion forum for the community of scientists and engineers working on development of intelligent devices.<br /> The objectives of the workshop will be to enhance the cross breeding of ideas, to compare concepts for incorporating intelligence in particle trackers, and to explore possibilities for application to other areas.<br /> The format of the workshop is on plenary sessions, for a duration of 2.5 days.<br /> This Workshop is the second of the series. The <a href="https://indico.cern.ch/conferenceDisplay.py?confId=68677" target="_blank"> first one </a>was held in Berkeley in 2010. <br /> Registration for the workshop will be <b>by invitation</b> following review of abstracts. <br /> The abstract submission deadline is <b>January 14, 2012</b>. <br /> Proceedings of the workshop will be published in <b>JINST</b>. <br /> Deadline extended to January 28, 2012. <br /> We invite submission of abstracts in the following subjects:<br /> *Applications of intelligent detectors<br /> *Coupled layer and monolithic architectures<br /> *Development of specific components<br /> *Electronic circuits (3D and conventional) on- and off-detector<br /> *High speed communication<br /> *System integration<br /> *Real time pattern recognition<br /> *Advanced Algorithms False INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-03T08:00:00 2012-05-05T18:00:00 2011-09-08T14:54:03 2012-07-19T06:36:21 Europe/Paris 56 false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] Applications of intelligent detectors Glasgow University tomasz.szumlak@agh.edu.pl Syracuse University (US) marina.artuso@cern.ch Glasgow University tomasz.szumlak@agh.edu.pl Glasgow c.parkes@physics.gla.ac.uk INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-03T12:30:00 2012-05-03T13:00:00 00:30 The LHCb experiment is dedicated to the search for new physics signatures in beauty and charm decays. The selection of interesting signal events requires accurate measurements of decay lifetimes and reconstruction of complex vertex topologies. The VErtex LOcator (VELO) has been designed to fulfill these functions, by providing tracking information close to the proton-proton collision region. At present analogue information from its readout electronic is digitized, corrected for various sources of coherent noise, and further processed through a series of algorithms implemented on FPGAs residing on the ìoff detectorî readout boards. The tuning of the parameters of these algorithms is performed using a bit-perfect emulation of these algorithms integrated in to the full off-line software of the experiment. These algorithms are described, and their performance and tuning in the course of the 2011 data taking cycle are summarized. For the LHCb upgrade in addition to the evolution to the present strip design a pixel option is also being developed. In both cases the zero-suppression functionality will be preformed by the read out front-end chip. For this a new ASIC is being designed - the chip will be a derivative of the TimePix/MediPix family. The chip will incorporate a local intelligence in the pixel for time over threshold measurement, time stamping and spare read out. In order to cope with the data rates and use the pixel area most effectively an on-chip data compression scheme will be implemented. This contribution will give an overview of the chip digital architecture, and describe the off-detector signal processing, including the time ordering and clustering. slides doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link paper doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link 2013-06-19 2013-06-20