154525 Conferences false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] Sezione di Pisa (IT) fabrizio.palla@cern.ch 15116 WIT2012 Workshop on Intelligent Trackers With the increasing capabilities of microelectronic technology, future particle detectors will be able to yield high level features that are not only simple geometrical positions or energy measurements in the sensors used. The ability to compute such high level primitives in near real-time is what we characterize as “intelligence”. This will enable the construction of detectors with novel functionalities, allowing the trigger logic or even the off-line analysis in experiments to handle immediately more complex features of the measurements. Two examples of new primitives are near real-time charged particle direction or charge clusters without pixel boundary effects. But the addition of such intelligence has practical challenges and in particular system issues must be addressed, such as material budget and power density. This Workshop would provide a discussion forum for the community of scientists and engineers working on development of intelligent devices. The objectives of the workshop will be to enhance the cross breeding of ideas, to compare concepts for incorporating intelligence in particle trackers, and to explore possibilities for application to other areas. The format of the workshop is on plenary sessions, for a duration of 2.5 days. This Workshop is the second of the series. The <a href="https://indico.cern.ch/conferenceDisplay.py?confId=68677" target="_blank"> first one </a>was held in Berkeley in 2010. Registration for the workshop will be by invitation following review of abstracts. The abstract submission deadline is January 14, 2012. Proceedings of the workshop will be published in JINST. Deadline extended to January 28, 2012. We invite submission of abstracts in the following subjects: *Applications of intelligent detectors *Coupled layer and monolithic architectures *Development of specific components *Electronic circuits (3D and conventional) on- and off-detector *High speed communication *System integration *Real time pattern recognition *Advanced Algorithms False INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-03T08:00:00 2012-05-05T18:00:00 2011-09-08T14:54:03 2012-07-19T06:36:21 Europe/Paris 59 false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] On-module electronic circuits (3D and conventional), intra-module and off-detector communication Radiation-Hard and High-Speed Parallel Optical Engine Prof. Ohio State University gan@physics.osu.edu Prof. Ohio State University gan@physics.osu.edu INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-04T17:00:00 2012-05-04T17:30:00 00:30 Parallel optical engine allows a compact design for high-speed data transmission. The design is enabled by the readily available high-speed VCSEL arrays. With the use of a 12-channel array operating at 10 Gb/s per channel, a parallel optical engine can deliver an aggregated bandwidth of 120 Gb/s. With the spacing of 250 mm between two VCSELs, the width of a VCSEL array is only 3 mm. This allows the fabrication of rather compact parallel optical engine for installation at a location where space is at a premium. We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector for the initial phase of the LHC luminosity upgrade. The ASIC is a 12-channel driver of a VCSEL array for operation up to 5 Gb/s. The ASIC is designed using a 130 nm CMOS process to enhance the radiation-hardness. A redundancy scheme has also been implemented to allow the bypass of a broken VCSEL. We have received the ASIC and the performance up to 5 Gb/s is satisfactory. We are able to program the ASIC to bypass a broken VCSEL. The power-on reset circuit is also successfully implemented which sets the ASIC to a default configuration with no signal steering. In addition, we are able to set the drive current in individual channels. We plan to port the design to the 130 nm SiGe BiCMOS process in order to operate at 10 Gb/s for an aggregated bandwidth of 120 Gb/s and some preliminary results of the design will be presented. slides Slides doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link paper Paper doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link 2013-06-19 2013-06-20