154525 Conferences false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] Sezione di Pisa (IT) fabrizio.palla@cern.ch 15116 WIT2012 Workshop on Intelligent Trackers With the increasing capabilities of microelectronic technology, future particle detectors will be able to yield high level features that are not only simple geometrical positions or energy measurements in the sensors used. The ability to compute such high level primitives in near real-time is what we characterize as “intelligence”. This will enable the construction of detectors with novel functionalities, allowing the trigger logic or even the off-line analysis in experiments to handle immediately more complex features of the measurements. Two examples of new primitives are near real-time charged particle direction or charge clusters without pixel boundary effects. But the addition of such intelligence has practical challenges and in particular system issues must be addressed, such as material budget and power density. This Workshop would provide a discussion forum for the community of scientists and engineers working on development of intelligent devices. The objectives of the workshop will be to enhance the cross breeding of ideas, to compare concepts for incorporating intelligence in particle trackers, and to explore possibilities for application to other areas. The format of the workshop is on plenary sessions, for a duration of 2.5 days. This Workshop is the second of the series. The <a href="https://indico.cern.ch/conferenceDisplay.py?confId=68677" target="_blank"> first one </a>was held in Berkeley in 2010. Registration for the workshop will be by invitation following review of abstracts. The abstract submission deadline is January 14, 2012. Proceedings of the workshop will be published in JINST. Deadline extended to January 28, 2012. We invite submission of abstracts in the following subjects: *Applications of intelligent detectors *Coupled layer and monolithic architectures *Development of specific components *Electronic circuits (3D and conventional) on- and off-detector *High speed communication *System integration *Real time pattern recognition *Advanced Algorithms False INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-03T08:00:00 2012-05-05T18:00:00 2011-09-08T14:54:03 2012-07-19T06:36:21 Europe/Paris 9 false [["minutes", "Minutes"], ["notes", "Notes"], ["paper", "Paper"], ["poster", "Poster"], ["slides", "Slides"], ["summary", "Summary"]] On-module electronic circuits (3D and conventional), intra-module and off-detector communication A Fast Clustering Block for Silicon Strip Seeded Track Trigger Mr. University of Pennsylvania mitch@hep.upenn.edu Mr. University of Pennsylvania mitch@hep.upenn.edu Mr. University of Pennsylvania nandor@hep.upenn.edu Mr. University of Pennsylvania EE dept. amoghh@seas.upenn.edu Dr. Lawrence Berkeley Laboratory mgarcia-sciveres@lbl.gov INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy

2012-05-04T15:00:00 2012-05-04T15:30:00 00:30 A viable seeded track trigger for a high rate collider detector environment must have excellent angular precision, response times commensurate with beam crossing rate and low mass. We have designed a fast clustering block servicing 128 contiguous strips to be included in an LHC upgrade silicion strip readout ASIC with these objectives in mind. The block is based on the presence of an analog front end with binary (threshold determined) strip readout latched at each beam crossing. Combinatorial logic tests for the presence of one or two adjacent strips over threshold, a cluster, at each beam crossing and records the seven bit address of up to two clusters via a high speed LVDS output. A correlator chip receives this data and looks for coincident hits between silicon strip layers. Since the clustering output will report the presence of one or two hit strips, a half strip width (~40um) resolution may be possible for each cluster. Our results show that the combinatorial clustering logic will settle within 6ns. Assuming a beam crossing rate of 40MHz, serialized data shifted out at 640MHz will meet the required beam synchronous update rate so that the correlator chip will receive cluster information delayed by a fixed offset of only two beam crossings. Present power estimates suggest that the fast cluster block with LVDS driver will consume less than 20mW. slides Slides doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link paper Paper doc http://indico.cern.ch/images/word.png word file ppt http://indico.cern.ch/images/powerpoint.png powerpoint file pdf http://indico.cern.ch/images/pdf_small.png pdf file odt http://indico.cern.ch/images/writer.png writer file odp http://indico.cern.ch/images/impress.png presentation file ods http://indico.cern.ch/images/calc.png spreadsheet file other http://indico.cern.ch/images/file_small.png unknown type file link http://indico.cern.ch/images/link.png link 2013-05-24 2013-05-25