The increase in the LHC luminosity and the reduction of the pixel size foreseen for the ATLAS pixel upgrade leads to an increased amount of data generated by the pixel detector at each beam crossing. The bandwidth of the readout should be upgraded to deal with this increase of data, to keep a good detector efficiency. Another approach, studied at LAPP, consists in decreasing the amount of data, by grouping adjacent pixels, thus forming clusters on the read-out chip. The analog center of gravity of the cluster can be determined directly inside the readout ASIC, and cluster can be classified at an early stage as "high Pt MIP-compatible" or not. Only the first category contains precise position information of interest to the tracking, and requires digitizing the barycenter position. The clusters in the second category contain only topological information and do not require digitization. In addition to the data reduction, the early availability of cluster positions of high Pt tracks can speed up trigger algorithms, The implementation of the local clustering algorithm takes advantage of TEZZARON 130nm 3D electronics, with analog readout of pixel, but it can also be applied to deep submicron 2D technology such 65 nm. The architecture will be detailed and the bandwidth will be compared to the one of more classical approach readout electronics.