FPGA and ASIC based algorithms for the present and upgraded LHCb silicon vertex detector
Presented by Dr. Tomasz SZUMLAK on 3 May 2012 from 12:30 to 13:00
Track: Applications of intelligent detectors
The LHCb experiment is dedicated to the search for new physics signatures in beauty and charm decays. The selection of interesting signal events requires accurate measurements of decay lifetimes and reconstruction of complex vertex topologies. The VErtex LOcator (VELO) has been designed to fulfill these functions, by providing tracking information close to the proton-proton collision region. At present analogue information from its readout electronic is digitized, corrected for various sources of coherent noise, and further processed through a series of algorithms implemented on FPGAs residing on the ìoff detectorî readout boards. The tuning of the parameters of these algorithms is performed using a bit-perfect emulation of these algorithms integrated in to the full off-line software of the experiment. These algorithms are described, and their performance and tuning in the course of the 2011 data taking cycle are summarized. For the LHCb upgrade in addition to the evolution to the present strip design a pixel option is also being developed. In both cases the zero-suppression functionality will be preformed by the read out front-end chip. For this a new ASIC is being designed - the chip will be a derivative of the TimePix/MediPix family. The chip will incorporate a local intelligence in the pixel for time over threshold measurement, time stamping and spare read out. In order to cope with the data rates and use the pixel area most effectively an on-chip data compression scheme will be implemented. This contribution will give an overview of the chip digital architecture, and describe the off-detector signal processing, including the time ordering and clustering.
Signal processing for the LHCb VELO detector and LHCb upgrade