A Fast Clustering Block for Silicon Strip Seeded Track Trigger
Presented by Mr. Mitch NEWCOMER on 4 May 2012 from 15:00 to 15:30
Session: On-module electronic circuits (3D and conventional), intra-module and off-detector communication
Track: On-module electronic circuits (3D and conventional), intra-module and off-detector communication
A viable seeded track trigger for a high rate collider detector environment must have excellent angular precision, response times commensurate with beam crossing rate and low mass. We have designed a fast clustering block servicing 128 contiguous strips to be included in an LHC upgrade silicion strip readout ASIC with these objectives in mind. The block is based on the presence of an analog front end with binary (threshold determined) strip readout latched at each beam crossing. Combinatorial logic tests for the presence of one or two adjacent strips over threshold, a cluster, at each beam crossing and records the seven bit address of up to two clusters via a high speed LVDS output. A correlator chip receives this data and looks for coincident hits between silicon strip layers. Since the clustering output will report the presence of one or two hit strips, a half strip width (~40um) resolution may be possible for each cluster. Our results show that the combinatorial clustering logic will settle within 6ns. Assuming a beam crossing rate of 40MHz, serialized data shifted out at 640MHz will meet the required beam synchronous update rate so that the correlator chip will receive cluster information delayed by a fixed offset of only two beam crossings. Present power estimates suggest that the fast cluster block with LVDS driver will consume less than 20mW.
Location: INFN Pisa
Address: Largo Bruno Pontecorvo 3 56127 Pisa Italy
- Mr. Nandor DRESSNANDT University of Pennsylvania
- Mr. Amogh AMOGH HALGERI University of Pennsylvania EE dept.
- Dr. Maurice GARCIA-SCIVERES Lawrence Berkeley Laboratory