Speaker
Ladislav Andricek
(MPS Semiconductor Lab)
Description
The DEPFET collaboration is in the final construction phase of a highly granular, ultra-transparent active pixel detector for high-performance vertex reconstruction at the Belle II experiment, KEK, Japan. A complete detector system is being developed, including solutions for ultra-thin sensors and their mechanical support, r/o ASICs, cooling, services, and a DAQ system capable of handling the huge amount of data coming from the pixel detector.
In this paper, the status of the DEPFET project is reviewed highlighting the milestone achievements in the construction of the Belle II pixel detector PXD. The main focus of this paper is the characterization of the recently finished pilot production of the sensors including the module assembly.
The sensor module is a silicon based multi-chip module (MCM) with the module substrate being the sensor wafer itself. There are three functional regions on the MCM: the 75 µm thin sensitive active pixel area with the DEPFETs in a two metal and two poly-silicon layer technology, the “end of stave” with three metal layers (two Al and one Cu) where the read-out electronic is placed, and the narrow long with the steering ASICs. Three types of ASICs are used: a mixed-signal ASIC as the analogue front-end and ADC, a digital data handling chip and a steering chip in HV-MOS technology for the row-wise addressing and clearing of the pixel matrix. There are 14 chips in total on the module, all bump-bonded to the sensor substrate, about 3000 bumps in total. In addition about 100 SMD components for supply line de-coupling and signal termination purposes are placed on the substrate.
The finished module has almost 200 kPixels and is read out at a continuous frame rate of 50 kHz via a wire-bonded and solder-attached flex cable. The whole detector will be assembled out of 40 modules, yielding a complex sensor system of about 8 Mpixels.
Our paper will describe the technology for the production of ultra-thin DEPFET sensor modules and discuss their performance on the test bench.
Primary author
Ladislav Andricek
(MPS Semiconductor Lab)
