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The monolithic pixel detector in high-voltage (HV) CMOS technology is a novel detector concept that has a few significant differences compared to the standard MAPS.
The HV CMOS detector uses lowly doped n-well/p-substrate diodes as charge collecting electrodes and relies on drift in their depletion layers as the main charge collection mechanism. This leads to relatively high MIP signals (when compared to standard MAPS) - typically 2200 electrons per cluster and an improved radiation tolerance. The unique feature of the detector is placing of pixel electronics inside the collecting electrode. This allows
100% fill factor even in the case when PMOS transistors are used. NMOS transistors can be also placed inside the collecting n-well using twin-well technology option. (Standard MAPS can use only NMOS transistors inside pixels, which limits pixel complexity.)
Last but not least, we believe that the detector concept can benefit from the new developments in high-voltage technologies that allow smaller transistor sizes and higher voltages.
High-voltage technologies are continuously developed and their long term availability is assured due to their application in flat panel-, printer- and automotive industry.
The tested detector is the first iteration of the demonstrator that should meet the typical requirements for a microvertex detector; it is a system of a chip that contains a 128 x 128 matrix (easily scalable to a larger size, e.g. 512 x 512) with 21 x 21 micrometers large pixels arranged as bricks, source-follower based- rolling shutter readout and in-chip ADCs that digitize signal amplitudes with 8-bit precision. The chip has digital outputs, which allows fast readout - typically 50 microseconds/matrix. Due to FPGA limitations, we have achieved so far the readout of a full matrix in 125 microseconds.
The detector concept has already been described in several publications. Here, we present for the first time the test beam results obtained with such a detector. The beam measurements have been performed using EUDET infrastructure; that is a telescope based on MIMOTel chip, EUDAQ data acquisition software and EUTel data analysis software. The measurements have been carried out on DESY and CERN.
The off line analysis is still in progress, we summarize here some preliminary results: we measure a most probable MIP cluster signal of 2200 electrons, spatial resolution of approximately RMS = 7 micrometers, single pixel signal-to-noise ratio of 13 and detection efficiency of more than 85%.
The non-ideal detection efficiency can be addressed to timing issues; the asynchronous readout of the telescope and DUT at high beam intensity leads to missed hits. Not all effects are understood yet, especially the measured spatial resolution is somewhat worse than expected. In the frame of EUTel software, new tools have been developed to investigate the detector properties such as spatial resolution, charge sharing, efficiency and the influence of the bricked arrangement on the pixel level.
The major drawback of the detector prototype is relatively high noise - input referred ENC is 90 e. The overall noise is however dominated by the end-of-column readout amplifiers and ADC noise, not by the detector itself and can be therefore easily improved. (The amplifiers used in the ADCs are rather unstable due to aggressive dimensioning of their filter components and in terms of their noise not optimal.) We expect to be able to double S/N ratio of the next detector iteration by simple means e.g. by increasing the shaping time constants or using nondestructive multiple readout.
Increasing of S/N ratio will certainly improve the performances of the next detector iteration.
Several detector chips have been irradiated up to 1e14 neq, they are still functional and the experimental results obtained with these chips will be presented as well.
In this paper we present for the first time the test beam results obtained with a monolithic particle pixel detector in a high-voltage CMOS technology.
