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TRAPPISTe-1 Monolithic Pixel Detector in SOI Technology
Lawrence Soung Yee, Elena Martin, Eduardo Cortina
Center for Particle Physics and Phenomenology
Universite catholique de Louvain
Louvain la Neuve, Belgium
Christian Renaux, Denis Flandre
Laboratoire de Microlectronique
Universite catholique de Louvain
Louvain la Neuve, Belgium
The TRAPPISTe-1 (Tracking Particles for Physics Instrumentation in SOI Technology) is the first in a series of pixel detectors built in silicon-on-insulator (SOI) technology. The TRAPPISTe series of detectors is a research and development project with a goal to study the feasibility of building particle detectors in SOI technology in which the detector and associated readout circuitry are fabricated together on the same substrate. TRAPPISTe-1 is being produced at the WINFAB laboratory at Universite catholique de Louvain (UCL)’s Ecole Polytechnique de Louvain. This first prototype will be tested to validate the detector architecture and evaluate its performance.
The UCL process is a 2 µm Fully Depleted SOI process. The SOI substrates consist of a thin top active layer in which circuits are made, a middle buried oxide layer (BOX), and a thick bottom p-type bulk handle layer. In order to build a monolithic detector, an opening is created in the BOX to allow access to the bottom layer. A 60X60 µm n-type implant is created through the hole to create the pn junction that will serve as the detector. The readout circuitry is created in the top layer around the opening and contact is made through the hole. Only a small area of the detector is covered with metal to allow for top side illumination of the pixel during testing. Finally, surrounding the detector and readout circuit is a 10 µm wide p+ guard ring.
To further understand the technology, a study of a photodiode developed with the same UCL SOI process has been performed. A square 500X500 µm^2 inter-digitated lateral PIN diode was tested by applying different bias voltages. The first set of tests involved varying bias voltages on the guard ring and on the back gate contact. Those results have shown that the leakage current of the structure is quite high, around 352 µA/µm2. The second set of tests studied the effect of applying a voltage bias on the top circuitry to deplete the substrate below. It has been seen that the leakage current is highly dependent on the top circuitry voltage. Testing with a laser is foreseen to study the charge collection of the device.
TRAPPISTe-1 consists of an 8X8 matrix of pixels, each with an area of 300X300 µm^2. The readout circuit for each pixel is based on the standard 3-transistor architecture used in pixel detectors. The architecture has been slightly modified to allow for a pipelined readout. The collected charge in each pixel is stored on a capacitor and subsequently read out column by column. Readout is controlled by a shift register implemented above the pixel matrix. The 64 pixels are divided into different groups. The outer set of pixels are reset structures which can be grounded for further isolation. The other pixels are divided into four groups each containing transistors with various threshold voltages Vt provided by the UCL process. Transistors with high Vt (0.77V/-0.95V), low Vt (0.24V/-0.08V), standard Vt (0.46V/-0.46V) and graded Vt are employed and the different pixel groups will be tested to see which gives the best performance.
TCAD simulations have been performed to study the depletion zones and charge collection. Of particular interest for future testing is the effect of the backgate bias voltage. It has been shown in other SOI based detectors that the bias voltage used to deplete the detector can have a significant effect on the operation of the circuitry in the top active layer. Signal formation was also computed, assuming carrier drift in the depleted zone and diffusion in the non-depleted zones. ELDO simulations of the readout circuit with various threshold transistors have been performed, with the calculated signal formation as input. Simulations show a gain of -4 V/V with a cutoff frequency of 270 kHz and a bandwidth of 1 MHz.
An FPGA based readout system is in development to control and collect data from the TRAPPISTe-1 chip. Tests with a laser set-up, as well as particle tests at the UCL Cyclotron facility, are foreseen. A write line connected to each of the pixels controls the storage of charge on to the pixel storage capacitors. Read and clock lines then control the integrated shift register which outputs each column of the pixel matrix one at a time. Each output is sent to a multi-channel ADC for digitization and eventual data storage on a computer. Testing is expected to begin in January 2010.
