######## # Alex ######## Automated test benches for the quarter chip Added testing of the slow serial readout path, this seems to be verified (the tdc is still partial behavioral model) Normal data path has been verified. Serial data patha has been verified. Option of loading test patterns into serializer has been verified. All these are the functional verifications before synthesis. VHDL test benches re-usable for gate level models. SEU tests are harder though