Workshop on Common ASIC for the LHCb Upgrade

4 Jul 2012, 08:30 → 6 Jul 2012, 17:30 Europe/Zurich

Krakow

Massimiliano Ferro-Luzzi (CERN), Tomasz Szumlak (AGH Univesity of Science and Technology (PL))

Meeting concerning the design and development of the common read-out chip for the LHCb upgrade The venue - Department of Physics and Applied Computer Sciences AGH - UST University of Science and Technology, ul. Reymonta 19 Building D-10, Room 123 (first floor) Evo connection will be available for this event Meeting Access Information: - Meeting URL http://evo.caltech.edu/evoNext/koala.jnlp?meeting=MMMeMn2M2uD9Di9D9MD29M - Password: The usual - Phone Bridge ID: 550 7386 Password: please contact me if you want to use the phone bridge Central European Summer Time (+0200) Start 2012-07-05 08:00 End 2012-07-05 20:00

more information directions.pdf

Wednesday, 4 July

14:30 → 19:30 Arrival

19:30 → 22:30 Workshop Informal Dinner

Venue "Polonia House" ("Dom Polonii") Main Square
Rynek Główny 14

Thursday, 5 July

08:30 → 08:50 Welcome/Introduction

Speakers: Massimiliano Ferro-Luzzi (CERN), Tomasz Szumlak (AGH Univesity of Science and Technology (PL))

08:50 → 10:50 Hardware Session I

Present situation and the LHCb upgrade plans - statements from the contributing institutes

Convener: Ken Wyllie (CERN)

08:50 Overview of the LHCb Upgrade - Electronics

Speaker: Ken Wyllie (CERN)

Slides TrackerASIC_workshop_050712.pdf TrackerASIC_workshop_050712.pptx

09:10 The LHCb Strip ASIC (Beetle) in Perspective

Specification, architecture (building blocks), simulation and tests Beetle experience Existing ingedients we could benefit from Open questions on the initial design specs

Speaker: Jan Buytaert (CERN)

Slides Strip_ASIC_Krakow.pdf Strip_ASIC_Krakow.pptx

09:40 Krakow ASIC activities

R&D + production schedule + costs for the new design Manpower (detailed involvement) Infrastructure in Krakow Sharing the design efforts with other institutes

Speaker: Marek Idzik (AGH Univesity of Science and Technology (PL))

Slides idzik_lhcb_cracow2012_06.odp idzik_lhcb_cracow2012_06.pdf

10:10 Manchester Contribution (Strip ASIC and Tell40)

Speaker: Prof. Chris Parkes (University of Manchester (GB))

Paper main.pdf

Slides

• Parkes_Krakow_06072012.pdf
• Parkes_Krakow_06072012.ppt
• pulseshape.pdf

10:30 Clermont Contribution (SiMP ASIC)

Speaker: Pascal Perret (Univ. Blaise Pascal Clermont-Fe. II (FR))

Slides krakow-LPC-120706.pdf

10:50 → 11:10 Coffee/Tea Break

11:10 → 12:10 Discussion session I

Financing - strategy and funding options
Review: schedule and spending profile
Keep in touch - regular meetings and reviews
Organization of activities
Define contact persons - Krakow and all subdetectors (VELO, IT, TT (CT)) other?

Conveners: Massimiliano Ferro-Luzzi (CERN), Pierluigi Campana (CERN-LNF)

12:10 → 13:40 Lunch

13:40 → 15:30 Hardware II

ASIC Design

Convener: Marek Idzik (AGH Univesity of Science and Technology (PL))

13:40 Front-end

Speakers: D. Przyborowski (AGH - UST), Marek Idzik (AGH Univesity of Science and Technology (PL))

Slides przyborowski_lhcb_krakow.pdf

13:55 6-bit ADC

Speaker: J. Moron (AGH - UST)

Slides LHCb_Moron_ADC6b.pdf

14:05 PLL and data serialisation

Speaker: M. Firlej (AGH - UST)

Slides pll_dll.pdf

14:15 FPGA and tests

Speaker: Szymon Kulis (AGH-UST)

Slides kulis_fpga.pdf

14:25 Analog integration

Speaker: Tomasz Fiutowski (AGH University of Science and Technology)

14:30 Digital processing and itegration

Speaker: Krzysztof Piotr Swientek (AGH Univesity of Science and Technology (PL))

Slides swientek_lhcb.pdf

14:40 Minimising overspill by signal shaping

Speaker: Jan Buytaert (CERN)

Slides Pulse_Shaping.pdf Pulse_Shaping.pptx

14:50 Processing Algorithms

Speaker: Tomasz Szumlak (AGH Univesity of Science and Technology (PL))

Slides processing_algos.pdf processing_algos.pptx

15:00 First ideas on transport protocol

Speaker: Lars Eklund (University of Glasgow (GB))

Slides VeloStripDataTransferProtocol_Krakow_5July2012.pdf VeloStripDataTransferProtocol_Krakow_5July2012.pptx

15:10 → 16:10 Software Platform

Emulation, calibration, monitoring and trending. Experience with the current software.
- New functionality
- What we can retain/re-use
- Brand new features

Convener: Tomasz Szumlak (AGH Univesity of Science and Technology (PL))

15:10 Core functionality of the VETRA++ platform

Speaker: Tomasz Szumlak (AGH Univesity of Science and Technology (PL))

Slides software_platform.pdf software_platform.pptx

15:40 VELO GUI - present monitoring

Speaker: Agnieszka Oblakowska-Mucha (AGH Univesity of Science and Technology (PL))

Slides GUI_AOM.pdf

15:55 VELOView - calibration trending

Speaker: Michal Adam Wysokinski (AGH Univesity of Science and Technology (PL))

Slides Velo_View.pdf Velo_View.pptx

16:10 → 16:30 Coffee/Tea break

16:30 → 16:50 Visit to the Lab

16:50 → 17:50 Discussion session II

Outcome of the meeting
- a list of technical issues and people responsible
- a scheme of collaborative work, list of roles, names and dates of meetings or reviews
- a list of versionable documents and names of persons responsible for each of them
- schedule/milestones, spending profile, specs, user guides, test reports
Do we need a MoU document (supported by the collaboration?)

Friday, 6 July

08:30 → 10:30 Discussion session III