APTS & DPTS Proximity & carrier boards discussion

Europe/Zurich
Videoconference Rooms
ITS3 WP3 weekly
Zoom Meeting ID
93697318437
Host
Miljenko Suljic
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    • 10:30 12:00
      Round table discussion 1h 30m
      Speakers: Andrei Dorokhov (Centre National de la Recherche Scientifique (FR)) , Mr Davide Marras (Universita e INFN, Cagliari (IT)) , Francesco Piro (EPFL - Ecole Polytechnique Federale Lausanne (CH)) , Franco Benotto (INFN - National Institute for Nuclear Physics) , Giacomo Contin (Universita e INFN Trieste (IT)) , Gianluca Usai (Universita e INFN, Cagliari (IT)) , Joao De Melo (CERN) , Leonardo Cecconi (CERN) , Paolo Camerini (Universita e INFN Trieste (IT)) , Wenjing Deng (Central China Normal University CCNU (CN))

      Brief summary of points discussed during the meeting. Points that need offline feedback [from indicated person] are marked with '?'

      Proximity card

      Presentation by Gianluca & Davide

      • Is the resolution of the proximity board DACs sufficient? [chip designers]
      • Is AD7386 ok choice for sampling the APTS signal? [chip designers]
      • DPTS: check that all, in particular control, signals are routed to the PCIe connector [Gianluca & Davide]

      Carrier cards

      Presentation by Franco & Matias

      • 4 layer board, layout optimized for as short as possible wire bonds
      • Less than 50 ns rise time on TRG speed (1.2V)
      • There will be no test points for signals neither on OA nor on SF version
      • Check mechanical constraints on the card size? [Miko]
      • Which decoupling capacitors on which lines? [chip designers]
      • HV/PW pin (pin 13, verified with Wenjing) to be routed to an independent LEMO connector, for HV biasing of AC structures.

      OA version

      • Is the heat sink under the chip required? [Walter]

      SF version

      • Buffers are needed on carrier card (single ended)
      • No dedicated effort is need in equalizing the traces
      • No metal under the central part of the chip (0.5x0.5 mm2), a hole (r = 0.25 mm) is desirable under the chip center
      • Bottom of the chip (central pad) should be connected to SUB

       

       

      Next meeting as soon as the preliminary board design is ready.