TWEPP 2021 Topical Workshop on Electronics for Particle Physics

Session

Programmable Logic, Design Tools and Methods

Sep 23, 2021, 12:20 PM

Conveners

Programmable Logic, Design Tools and Methods

• Johan Alme (University of Bergen (NO))

Programmable Logic, Design Tools and Methods

• Johan Alme (University of Bergen (NO))

42. Hog: handling HDL repositories on git

Davide Cieri (Max Planck Society (DE))

9/23/21, 12:20 PM

Programmable Logic, Design Tools and Methods

Oral

Handling HDL project development within large collaborations presents many challenges in terms of maintenance and versioning, due to the lack of standardized procedures. Hog (HDL on git) is a tcl-based open-source management tool, created to simplify HDL project development and management by exploiting git and Gitlab Continuous Integration (CI).

Hog is compatible with the major HDL IDEs...

109. PAM-4 implementation study for future high-speed links

Chaowaroj Wanotayaroj (CERN)

9/23/21, 12:40 PM

Programmable Logic, Design Tools and Methods

Oral

With the ever-increasing amount of data from HEP experiments, the transmission rates must keep up. To mitigate the exponential growth of the total loss due to the increased frequency, the 4-Level Pulse-amplitude Modulation (PAM-4) could be envisaged, allowing to reach 56 Gbps or even 112 Gbps in extremely high-end applications. A system using PAM-4 encoders and transceivers has been built...

18. Hough-transform-based FPGA track processor for the ATLAS experiment at CERN

Tong Xu (Argonne National Laboratory (US))

9/23/21, 2:00 PM

Programmable Logic, Design Tools and Methods

Oral

The Hough-transform-based FPGA track processing is considered for the trigger system of the ATLAS detector at the Large Hadron Collider at CERN as a part of the upgrade for the High-Luminosity program. The prototype firmware has been developed to evaluate system size. The track processing is organized as a pipeline to increase data processing and clock rates. This Hough transform accumulator...

32. Automated firmware generation and continuous testing for the CMS HGCAL trigger primitive generator

Jean-Baptiste Sauvan (Centre National de la Recherche Scientifique (FR))

9/23/21, 2:20 PM

Programmable Logic, Design Tools and Methods

Oral

A first version of the firmware blocks of the trigger primitive generator for the CMS endcap calorimeter upgrade (HGCAL) are being implemented, in order to assess the FPGA resource requirements and dimension the system. For the development of some of these blocks, a data-driven design flow is used to automate the production of multiple firmware variants based on VHDL and HLS C/C++ templates....

12. FPGA implementation of RDMA for ATLAS Readout with FELIX in High Luminosity LHC

Matei Vasile (IFIN-HH (RO))

9/23/21, 2:40 PM

Programmable Logic, Design Tools and Methods

Oral

The FELIX system is used as an interface between front-end electronics and commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. RDMA communication is implemented using software on both end of the links. Exploring opportunities to improve data throughput as part of...