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Feb 21 – 25, 2022
Vienna University of Technology
Europe/Vienna timezone

FPGA-based 100G network readout solution for SHINE pixel detector

Not scheduled
Vienna University of Technology

Vienna University of Technology

Gusshausstraße 27-29, 1040 Wien
Recorded Presentation Electronics


Cong He (Institute of high energy physics)


With the progress of semiconductor technology, the spatial resolution of pixel detector in high-energy physics experiments is improving continuously, at the same time, the amount of data generated is also increasing rapidly. In Shanghai HIgh repetition rate XFEL aNd Extreme light facility (SHINE), the data rate of its high frame rate pixel detector is expected to exceed 1.6 Tbps in the future. Traditional gigabit and ten-gigabit networks can no longer meet readout demand and the transmission rate of readout system has become a bottleneck. Obviously, it is necessary and significant to develop a network with higher bandwidth. Combined with the current situation and the needs of upgrading, we developed two 100G readout solutions on FPGA. The first solution, NET-CONV, can extract the raw data from the network packet and converge data stream from multiple 10G links into single 100G link. It supports parallel transmission of up to 12 channels and achieves a total peak rate of 94 Gbps in the test. To further improve the transmission speed of single Ethernet port on readout board, the second solution, NET-TOE, is developed. It implements a complete network protocol stack at 100 Gbps line rate, supporting maximum transmission unit (MTU) adjustment, TCP window scale and UDP. The actual measure shows that the stable transmission rate of the firmware can reach 97 Gbps.

Primary author

Cong He (Institute of high energy physics)


Jie Zhang (institute of high energy physics) Xiaoshan Jiang (institute of high energy physics)

Presentation materials