Speaker
Description
The TPSCo 65 nm ISC technology is under study in the framework of the CERN-EP on monolithic active pixel sensors (MAPS) for High Energy Physics (HEP) applications, and the ALICE ITS3 upgrade project, for which a wafer-scale stitched MAPS sensor is under development. This contribution presents designs and measurement results for Bandgap Reference (BGR) and Temperature Sensor (TS) prototypes needed for this large chip, but also more largely applicable. Simulation results of the design of Low Drop-out Regulator (LDO) to be submitted for the next prototyping run will also be discussed.
Summary (500 words)
The BGR circuits are commonly used to provide reference voltage (V$_{ref}$) which is ideally insensitive to process, temperature and power supply variations. Additionally, for our application, BGR circuit must be tolerant to the total ionizing dose (TID) effects. We prototyped BGR circuits based on 4 different flavors of reference elements such as conventional diode, BJT, gated-diode and DTMOST [1]. All circuits were found to be functional. The measurements demonstrated that the value of V$_{ref}$ changes in the range of 462 mV ${\pm}$ 0.5 mV when power supply voltage is swept from 1 V to 1.3 V for the best type of BGR circuit (DTMOST-based). The temperature scan measurements show that DTMOST-based BGR has the lowest variation of the value of V$_{ref}$ (475 mV ${\pm}$ 0.3 mV) when temperature varied from -20 $^{\circ}$C to 40 $^{\circ}$C. The temperature gradient of BGR can be adjusted according to different process corners by means of 8 configuration bits. The measurements of DTMOST-based BGR during X-ray irradiation show that the value of V$_{ref}$ of BGR varies within 1.5-2${\%}$, and this variation is the least among 4 flavors of BGR.
Temperature monitoring on the chip is essential for having control of the performance of the chip. We designed Temperature Sensor (TS) circuit with 2 different flavors of reference elements such are conventional diode and BJT to monitor temperature changes in the range from -30 $^{\circ}$C to +110 $^{\circ}$C. The measurements show that the output voltage of the TS circuit provides a 1 mV/$^{\circ}$C gradient within the specified temperature range.
The LDO circuit is an essential component to provide stable power supply voltage for power supply-noise sensitive blocks such as Phase Locked Loops (PLLs). The high frequency voltage spikes up to 100 mV can be present at the input of the LDO circuit. These spikes must be suppressed down to the level of 1 mV. Generally, LDOs use large off-chip output capacitors (C$_{load}$) in order of tens of ${\mu}$Fs. For our design, we choose Output Capacitor-less LDO (OC-LDO) to avoid any external components. The LDO circuit is based on Flipped Voltage Follower architecture. The circuit is powered by 1.32 V supply voltage, and drop-out voltage is 200 mV. The circuit is designed to operate with 1.5-2 mA load current. This circuit covers 200 ${\mu}$m $\times$ 68 ${\mu}$m on a die. Post-layout simulations show that Power Supply Rejection Ratio (PSRR) of the LDO circuit is -59 dB in the low frequency range up to 1 kHz. In the high frequency range, PSRR of LDO is significantly worse which is -5.5 dB as its lowest at 5 MHz. The presentation will describe the circuit design and go in detail on the measurement results.
Reference
[1] . V. Gromov, A. J. Annema, R. Kluit, J. L. Visschers, and P. Timmer, “A radiation hard bandgap
reference circuit in a standard 0.13 μm cmos technology,” IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2727–2733, 2007.
