Summary 500 words
For the upcoming upgrades of the ATLAS pixel detector, different powering schemes are investigated to maximize efficiency and minimize material. For the Insertable B-layer (IBL) project, the use of direct powering as in the present detector is envisaged for system compatibility. However the addition of on-chip linear regulators is necessary. Regulators with a maximum allowed input voltage higher than the one of the chip are used to allow for higher voltage drops on the cables (Vdrop = Vmax – Vnominal), and thus reduce the cable cross section to match space and material budget constraints. For Phase 1 upgrade, a replacement of the entire pixel detector is proposed, where a possible powering option is serial powering. In this scheme the detector modules are powered in series via a constant current. On-chip regulators generate the necessary analog and digital voltages out of the current supply. To add redundancy and robustness to the scheme, the regulators operate in parallel at module level.
In this framework the use of the Shunt-LDO regulator is proposed to power the new ATLAS pixel front-end chip designed for IBL and Phase 1 upgrade, the FE-I4. The Shunt-LDO combines the capability of Low Drop-Out (LDO) regulators to generate a constant supply voltage, with the feature of shunt regulators to assure a constant current flow through the device. In full Shunt-LDO mode, it offers the optimal solution for the serially powered detector systems. With respect to a standard shunt regulator in fact, the Shunt-LDO design is more robust against process variation and mismatch, allowing for safe parallel operation. Given the integrated LDO functionality, regulators generating different output voltages can be placed in parallel, whilst the shunt circuitry allows coping with increased input current, should one of the parallel placed regulators fail. In addition, for powering schemes requiring linear regulators, the Shunt-LDO can be used in pure LDO mode by switching off the shunt circuitry. Although the regulator is designed with thin-gate oxide transistors in a commercial 130nm CMOS technology, cascoding was used in every branch of the regulator to allow for an input voltage of 2.5V.
After two successful prototyping runs confirming the working principle and showing good results, the Shunt-LDO regulator has been integrated in the first engineering run of the FE-I4, the FE-I4A. Two regulators per chip allow studying the use of the Shunt-LDO to power the next generation of pixel detector modules with FE-I4.
After an overview of the proposed powering scheme for IBL and Phase 1 upgrade, with focus on the regulator requirements, the Shunt-LDO will be presented. Results of single device characterization, in full Shunt-LDO and pure LDO modes will be discussed. These include line and load regulation figures, as well as load transients, temperature dependence, and possibly performance after irradiation. The performance of the FE-I4 chip, in particular in terms of noise, will be compared for different powering options: direct, Shunt-LDO, and LDO powering. Finally, the results of module characterization with Shunt-LDO powering will be shown.