Summary 500 words
The silicon pixel detector (PXD) developed by the international DEPFET collaboration consists of 20 DEPFET modules being readout independently (though synchronously) by the ASICs chips directly bump bonded on each module. Sensors are read-out row-wise with a frame rate of 50kHz. After digitization, the total raw data rate will be around 80Gbps/half module. To cope with these data rates a zero suppression is necessary. The Data Handling Processor chip (DHP) implements the zero-supression and dedicated data processing algorithm to correct for pedestal and common-mode offsets. Futhermore it synchronizes and controls switchers and drain current digitizer (DCD) chips.
All the raw data is being continuously stored into the chip memory. To optimize the chip efficiency, DHP chip processes that data only if the trigger signal is received. Upon the trigger arrival, the processing of the previously stored data starts, hits are recognized and sent to the chip output.
The chip is being implemented using the 90nm technology. In this talk conceptual solutions and latest results from the first test chip will be presented.