1) SR read back tests - Bonn, SLAC 2:done) Efuse programming. - LBNL 3) Shuldo operation. Powering chip through Shuldos. Also Shuldos used as standard LDO. -Bonn 4: done- DCDC excluded for IBL) DC-DC operation. Powering digital or analog through DC-DC. - LBNL 5:done) Temperature dependence of threshold. Different VTH generation options and temperature dependence of each. - LBNL 6) Stop mode operation. Tests of region memory. Fill all 5 memories, test all latency values. -Bonn 7: done) Measure digital current as a function of memory occupancy -Bonn, LBNL 8) Timewalk measrements vs. front end bias settings. Timewalk dispersion over array. Small hit recovery vs. digital threhsold settings. - LBNL 9) Implement monleak scan (needs external instrument).- Goettingen 10:done) Characterize all bias DACs over their full range. - LBNL 11:done) Studdy PLL - Bonn 12) Repeat some PLL tests after irraidation - LBNL 13) Study operation with regenerated 40MHz clock instead of raw clock -Bonn 14) Addition of external ref-clock to USBpix so we can test operation with realistic clock - Bonn 15) Low threshold characterization. - will be done by everyone testing sensors 16:done) Chip threshold tuning with TDACs. -Goettingen 17: done) Usage of alternative SR. -SLAC *** 18) CPPM columns. 19:done) Self triggering mode. Self trigger scan -Goettingen, Bonn *** 20) Look at service records coming out. Cause errors on purpose. What errors are coming out normaly? 21) Analug muxes at the to of the chip -CPPM 22:done ) Better characterization of pulser. -SLAC, LBNL 23) Power supply rejection ratio. -NIKHEF 24) Fully exercise and validate scan chanis. -NIKHEF *** 25) Analog power vs. performance 26:done) Determine external TDACVbp resistor value - LBNL 27: done) Precision comparison of threshold dispersion and noise between VNCAP columns and nominal columns. Is there any change with temperature? - LBNL 28) Collect all wafer probing functionality into single software - Goettingen 29) Measure limits of operating frequency and voltage. Where do things stop working? - NIKHEF 30) Calibration of charge scale - all 31) Calibration of pulser timing delay and T dependence - LBNL *** 32) Check if reset lines are needed for powerup. Try appling power with different ramp speeds with the reset pads floating. *** 33) Classify serice records in output data stream. Which records come out and when? What circumstances lead to FIFO full, for example, so that it can be reproduced in simulation. *** 34) Check skipped trigger counter- register 41 *** 35) Measure phase difference between ref_clock and SR clock ouptut of I/O mux. Wnat to know how much it vaires from column to column. *** 36) Check that giving a few scan chain clocks puts EOCHL in funny state and causes BCIDs to come out in incorrect order. *** 37) Module operation. Pull all wire bonds that will be floating in module flex and verify startup and operation.