TSU CONS Reliability Meeting - 1

Present: M. Blaszkiewicz, L. Felsberger, J. Uythoven, N. Voumard

Minutes

N. Voumard presented a comprehensive overview of the current and future TSU systems to explain the general concept and differences between the two versions. In addition, several additional aspects were discussed, briefly outlined below.

Layout

• Powering for TSU is provided via UPS units from separate power sources.
• Voltage surveilance is present in the line between TSU and Trigger Delay unit - if a cable is, e.g., disconnected, it will trigger a synchronous dump via Slow Control (PLC) and via the TSU. The feature is tested on a regular basis by cutting the UPS.
• The TDU shown in slide 10 of 2022 Dec BISv2 Status and Actuator Board Presentation (cern.ch) is a different one that the Trigger Delay unit in the schematics of the shown presentation.
• There are 48 outputs of the Trigger Fan Out unit, some of which go to the LBDS Generator and some to other destinations.

TSU Card Detection and Synchronization

• The logic will be entirely moved to the FPGA.
• External watchdog will trigger an asynchronous beam dump in case of loss of configuration in the FPGA. Additionally to the asynchronous dump on the faulty card, a synchronous dump is issued by the other TSU (the not-faulty one). An asynchronous dump can be issued only if both cards are faulty at the same time.
• Communication between TSUs will be performed on the same FPGA. 

TSU User Permit to BIS

• The idea to enable the arming procedure is to force the the permit to true at first, so that it can be used to allow arming.

Actions

1. Schedule a bi-weekly meeting to keep everyone updated in terms of the study's progress.
2. Begin the top-down analysis, which at first will focus on architectural aspects of the new system; specifically addressing major changes between the old and the new versions. 
3. Consider options for formal verification methods to be applied to the FPGA firmware testing.