BISv2 Reliability Study Progress Meeting - CIBDS

Present: M. Blaszkiewicz, A. Collinet, L. Felsberger, I. Romera Ramirez

Minutes

The meeting was a recap of the early advancements completed some time ago for the CIBDS board and next steps. 

Top-level functions FMECA

We agreed that the main functions of the CIBDS is: to generate an asynchronous dump request via the TDU, to pass on the BIS beam permit loop signal, to interpret the Link Mode and trigger asynchronous (via TDU) and synchronous (via beam permit and TSU) beam dump requests.

Functional Block Diagram

The main signal flows are as shown in the slide. There are some modifications: there are links between Monitor FPGA and Critical FPGAs, as well as there is a software link mode singal which is received in the monitor FPGA and passed on to the critical FPGAs.

FMECA

A further discussion of the top-level functions, possible failures, their effects and criticality was one of the highlights of the meeting. The list of identified failures is as follows: 

• Blind failure (single path).
  • Blind sync - not generating asynchronous dump request.
  • Blind async - not generating a synchronous dump request.
  • Blind - not generating asynchronous nor synchronous dump requests.
  • Link mode.
    • Blind sent ext - not sending external dump request.
    • Blind generate ext - not generating dump request upon receiving an external dump request when link mode enabled.
•  False dump.
  • False dump async - spuriously generate ONLY asynchronous dump request.
  • False dump sync - spuriously generate ONLY synchronous dump request.
  • False dump - spuriously generate asynchronous and synchronous dump requests.
• Maintenance
• No effect. 

Firmware verification methods

It was agreed that firmware verification would be an interesting development for the FPGA-based projects. AC suggested that the Equivalency Checking is of particular interest to him, while formal verification methods can prove to be a time-consuming and effort-intense activity. We will follow up on those points further.

Questions

• Q1. Transistors' applied voltage is generally 3.3V.
• Q2 and Q4. Assignment of the 217Plus categories to the actual components requires further scrutiny. 
• Q3. Generally 50% derating is acceptable, but we will look further at capacitors with highest stress value.

Actions

1. Update and share FMECA tables for CIBDS and CIBF SFP.
2. Take a look into past CIBDS studies of BISv1.