BISv2 Reliability Study Progress Meeting - CIBDS

Present: M. Blaszkiewicz, A. Collinet, L. Felsberger  

Minutes

Presentation featured statistics of the CIBDS FMECA.

Brownout condition was mentioned by LF; AC replied that it is not relevant as BPL can be stopped always. 

Project statistics

The numbers are similar to other BIS projects. There was a short discussion of capacitors - their operating voltage is almost always 3.3V, aside from some 12V around TDU triggering.

Blind failures

The first blind failure, the one connected to the FPGA, actually requires another failure to take place before it is actually a blind failure in both, asynchronous and synchronous paths.

The second blind failure, of an oscillator, remains in this category as the counters and similar elements may not work anymore - and prediction of likely end-effects is difficult, however worst-case scenario is a blind failure. Mitigation:

• All FPGAs in the BIS have phase locked look (also considers natural change, see the datasheet)
• Auto-correction based on PPS (for monitoring FPGA)

Additional matter was a FPGA junction temperature which is an important factor to predict its failure rate. AC confirmed however that 55C is a reasonable assumption. In the lab, only the ambient temperature is monitored - an it is 30 C for this card. 

Blid sync indication in the FMECA table means NOT requesting an asynchronous dump (and the opposite for blind async).

Link Mode

• Hardware link goes via backplane connection to CISU.
• Logic of generating STOP is done in the receiving CIBDS.

False dumps

"False dump async local" is essentially no effect: it signifies sending a spurious dump request in the local mode (i.e., during testing).

Next steps

1. Check IC19 component.
2. Double check what TSU does with feedback (whether it is in the remote or local mode).
3. CIBDS report to be created.