BISv2 Reliability Study Progress Meeting - CIBAB

<h1>BISv2 Reliability Study Progress Meeting - CIBAB</h1>
<p>Present: M. Blaszkiewicz, A. Collinet, L. Felsberger, T. Podzorny, I. Romera Ramirez  </p>
<h2>Minutes</h2>
<p>The meeting was started with the comparison of various failure rates assigned to a specifc transistor selected as a study case. Details are shown on the slide 8.</p>
<p>The next block was a discussion of all comments made in the FMECA by AC:</p>
<ul>
<li>J3, J4, J5 are handling differential connections, therefore a blind failure would happen there only if there is a double failure: both in positve and negative signals. When only one of those is wrong, then there will be a beam dump.</li>
<li>When Post Mortem fail, the "false dump" is indicated there as a loss of availability, even though there might be no immediate dump.</li>
<li>Artix 7 open will lead to a false dump immediately</li>
<li>CIBU cards will be tested only once per year, as it is only one client that triggers the dump every time. It means that some of them will be tested only during Technical Stops.</li>
</ul>
<h2>Next steps</h2>
<ol>
<li>The first next step is to create a report as for all other BISv2 boards in the study.</li>
<li>The quantitative results to be used in the global model of the BISv2. </li>
<li>for research interest: compare prediction standards for buffers (logic transistors) with transistors (suspected power applications)</li>
</ol>