Univ. EE Controls Reliability Study - 2

<h1>Univ. EE Controls Reliability Study - 2</h1>
<p>Present: M. Blaszkiewicz, L. Felsberger, B. Panev</p>
<h2>Minutes</h2>
<p>The meeting's objective was to present the results of the failure rate prediction step for the EE UC boards and decide on the next step - the end-effects assignment. It started by LF recounting the state of the study and completed work. Then, as shown in the slides, an introduction of the study methodology proceeded, followed by results of the failure prediction step for three EEUC boards: Controls, Driver, FPA SPA. </p>
<p>The next part was a summary of the hybrid MC simulations. They will be updated accordingly, following the issues discussed as well as new FITs estimations only with relevant components, after getting the list of those from BP. </p>
<p>A number of additional observations has been made throughout the presentation:</p>
<ul>
<li>Through holes, fiducial targets - confirmed that can be left at 0 FITs; mostly used when card is taken out of the tunnel to a tester.</li>
<li>TVS diodes are protecting the FPGA; that one gets voltages of 1.2V, 2.2V and 3.3V. </li>
<li>UBS Interface in the Controls Board will be used only for diagnostics when someone obtains access. Not to be used during operation.</li>
<li>The critical path is supposed to be composed of the FPGA, Powering, some logic gates. LEDs are not critical, and buttons will be largely removed.</li>
<li>EEPROM will be used to keep track of information about the PCB, its unique coding, where it is, has it been used, etc. Provides information through a communication card to the outside. </li>
<li>Fuses are used for protection against radiation deterioration - are much higher than rated current.</li>
<li>According to BP, regulators - all components are tested in the BECO Radiation to Electronics. They will be tested in CHARM as well.</li>
<li>Switches will be used only for configuration; still, some of them will be critical. All switches in PCBs here are DIP.</li>
<li>Push buttons in FPA SPA will stay.</li>
<li>There are 4 optocouplers - 2 going to CNTL 1, 2 going to CNTL 2.</li>
<li>Interlock board is reporting to the control cards. 
<ul>
<li>CNTL to FSPA rupture the FPA loop.</li>
</ul>
</li>
<li>CERN bPOL12V - raised the point about recommendations, BP said they will try to go below 12V.</li>
<li>Tantalum derating.  </li>
</ul>
<h2>Actions</h2>
<ol>
<li>Send a list of components to BP, add interlock card.</li>
<li>BP will prepare a list of components relevant to the critical failure path - only in the most critical configuration.</li>
<li>600A type circutis - to be checked if EE opens the FPA loop.</li>
</ol>