Univ. EE Controls Reliability Study - 3

Present: M. Blaszkiewicz, L. Felsberger, B. Panev

Minutes

Design for each board has been analysed separately, here are the highlights gathered:

FPA/SPA

Critical pages: Connectors, Interlock Loop A, (Interlock Loop B too, but not used).

- Also has push buttons & remote connection.
- Makes multiple connections besides FPA/SPA.
- Also creates commands:
  - open, close, reset,
  - fpa, spa goes separately.
- Opening the loop also done.

Interlock

Critical pages: Buffers, Connectors, Interlock channel (x15).

- - How many ones are critical depends on the EE system:
    - vacuum - 15 critical,
    - 600a - ?.

Driver

Critical pages: all aside from power supply and P1 (+ lower side of the page).

- open --> or gate
- close --> and gate, also done at the level of two driver boards (by routing in series)
- dip switch - selects OC or relay (only for ch1 and ch2)
- each system uses 7-8 channels, 13 ka maybe all
- active opening of drive for vacuum switches --> have to immediately open them --> is on the interlock card --> sensing on the switch input voltage side and chassis
  - capacitors monitored

Control

Critical pages: FPGA Banks (x2), FPGA, Backplane Connector P1, P2, P3.

- Reset FPGA will also open switches beforehand.
- Closing of switches is not allowed during reset.
- When FPGA clock stops, switches are opened.
- Very little of FPGA capabilities used.
- Undefined voltage - not clear.
- ID part is for card only - not for configuration of fpga - not critical.
- Multiplexer - not critical - jtag, usb, programming interface.
- P6 (or P5): possibly to have CNTL card cross-communication.
  - also to notice in idle when one card is missing.
- P4 - analogue measurements - not an interlock
  - interlock is thermostat - in parallel.
- USB - debugging and programming only for closing switches

Timeline

February, March - design office for series production

Actions

Establishing a failure rate for critical components only.