SoC Interest Group Meeting: Demo/Presentation

Friday Mar 15, 2024, 1:30 PM → 4:30 PM Europe/Zurich

222/R-001 (CERN)

222/R-001

CERN

200

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Christos Gentsos (CERN (IT-CA-GES)), Hamza Boukabache (CERN), Ralf Spiwoks (CERN)

65172635208

Ralf Spiwoks

Adrian Byszuk

- 1:30 PM → 4:30 PM
  MathWorks SoC Design Flows @ CERN 3h
  
  This 3-hour workshop, presented by experts from MathWorks, offers a deep dive into the latest applications and best practices of Model-Based Systems Engineering (MBSE) and Model-Based Design (MBD) for System-on-Chip (SoC) design flows.
  
  Attendees will gain hands-on experience in floating point to fixed-point conversion, automatic code generation workflows for Field Programmable Gate Arrays (FPGAs) and SoCs, and optimizing code for performance. The workshop is specifically tailored for algorithm, system, and hardware engineers involved in configuring models for Hardware Description Language (HDL) code generation for deployment on FPGA, SoC, or Application-Specific Integrated Circuit (ASIC) platforms.
  
  Speaker: Stephan van Beek (MathWorks)
  - Introduction 15m
  - Systems Engineering Workflows for FPGA/SoC 15m
    
    • Managing Requirements
    • Function allocation to SoC platforms
  - Automatic HDL Code Generation and Verification 1h 15m
    
    • Converting Floating point to Fixed-point
    • Generating IP cores including AXI-interfaces
    • Verifying HDL code using HDL co-simulation (QuestaSim/Vivado)
  - Deploying Algorithms on SoC Platforms 1h
    
    • Real-Time Code Execution Profiling
    • Generating Target-aware C-code for ARM
    • Full Algorithm Deployment on SoC
  - Summary and Next Steps 15m