• jens away 19/07 - 20/08, david away 20/08 - 30/08 (hand over all infos), me away 30/08 - 09/09 & 13/09 - 20/09 - 7. oct HL annual meeting "Reliability studies on PDSU and PDSU-BIS concentrator interface"
  • prepare PDSU estimates and questions & models until 20/08 - until 30/8 prasenation Draft
  • DSP decoupling capacitors
    • short --> would need to check what fpga does
    • fpa w/o core voltage - only via external baustein
    • if core voltage gone - no proper data out at start of fill
  • check will by per fill
    • fpga lives and is configured
    • not sure whether cable to quench heater is properly sone
    • such check should cover majority of blind failures on digital platform
    • can also ask tomasz
      • is supply voltage monitored?
      • could detect lots of faults
  • blind failures
    • active triggers
    • current loops not really
    • channels not really
      • almost all safe
  • send fmeca templates
  • v3 - fpga card ready -
    • pdpack v2 - is the same for pdsu - tomasz
    • channel in autumn (but no big changes) - very similar to pdsu cliq - very different for hds - jens
      • re-used for big CONS in LHC
      • but send current
    • trigger (very different pdsu) - jens
      • version exists
    • midplane
  • blind failures during yearly tests - no consistent record