• last UQDS version --> trigger separately
• input stage
  • more resistors for voltage withstand
  • short in voltage tab --> inductive heating ..> burns short away
  • ground floating
    • inductive via PS
    • digital via coupler
  • voltage protection
    • FETs stop - current limiter
    • blind failure potential
  • from top comes gain control
  • test signal as soon as differental converter
  • differential for ADC
    • reduces signal to noise
  • high voltages
    • from magnet - shortly
    • ESD - test by not caring in lab about it
      • there were families of insulators who had problems
  • exchange
    • monitor via busy signal
    • state machine to check if busy is not ready
    • if too long not heard back --> safe signal
    • also check if noise is still present --> otherwise trip
  • flash memeory
    • calibration of channel
      • offset (not important)
      • gain error
    • but communicated to high level software
  • voltage reference - failure--> wrong data
  • in principle
    • separate power etc
    • poweer pins shared
    • steckverbinder geshared
• midplane
  • lots of plugs
  • diagnostic not present
  • most connectors for input channels (16 x 5)
• trigger
  • all options, maybe not all mounted
  • 4 current loops
    • optionally source
  • up to 8 hds/pdsu triggers
    • depletion mode FET
      • safe against short pulling down 15V line
    • because triggering needs to be active
  • contact problems?
    • contact line across first and last pin
    • because IT won't trigger often enough to see
  • sync
    • tell post mortem to synchronize
    • 10 uQDS
      • one detects, tells others
    • off topic - force A/B
      • boards swap sending
      • tell controller to stop toggling
      • for continous logging
  • fpga not directly driving, hence buffers (in middle)
  • vdp
    • fpga
      • no clock
        • communcation still there, but only static function
        • no protection
        • clk err has monitoring --> triggers FPA via FPGA
        • currenlty not foressen, but may be added
    • debug interface
      • either spi or uart
      • uART directly to fpga
      • spi via uC
        • spi also to uart
    • uC
      • connection to fpga only via handful of pins
      • all settings go to fpga
      • can write thresholds at any time
      • reads all registers periodically and writes out
        • track record is there
        • SPI for Laure?
        • SIS could do periodical check?
      • configuration management may need update
        • LSA has config
      • fpga has column parity over register map
        • if uC starts doing wild things
        • should notice parity
        • fpga has no clue what machine does
      • if uC fails safe, FPGA keeps going
    • memory
      • local configuration stored on flash
    • local PSU
      • shorts of cap - power supply goes down
      • should lead to FPA open
      • 1.7V instead of 3.3. --> fpga does whatever
      • all components can cause
      • ceramic capacitors
        • one known case at cern
• ps
  • one big ac dc (5V)
    • several dc dc
    • 3.3 v
  • adc for voltage monitoring
    • for all rails jeweils fuer a und b
  • availability vs protection trade off
    • impossible to keep fpa loop closed when current gone
  • only protection
    • if monitoring gone, could enter intermediate stage, fpga ould do weird things
• uQds as PDSU trigger when spurious triggering
  • rather on the slow side; could be adjusted to be fast enough but then we may do too many spruious triggers