Conveners
Verification
- Mathieu Saccani (CERN)
Verification: 2
- N. Engelhardt (YosysHQ)
Verification: 3
- Tom Williams (Rutherford Appleton Laboratory (GB))
This talk explores the synergy between VUnit and UVVM, two leading open-source
verification frameworks for VHDL. UVVM provides a structured approach with powerful
testbench utilities and verification components, while VUnit enhances automation,
advanced test management, and continuous integration support. Additionally, VUnit
enables seamless use of multiple simulators within a single...
Requirements Tracking is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space and Avionics) applications.
Unfortunately, this is often handled manually, which is very time-consuming and error-prone. The open Source UVVM’s Specification Coverage allows a really efficient collection of predefined requirements, and it generates the...
Testing an FPGA design is complex and time consuming. Testing the main payload of an ESA mission spacecraft much more so. While modern HDL languages have powerful test capabilities, they can hardly match the unbounded facilities provided by Python. We have thus devised a flexible, cocotb-based framework for the task, in which JSON files are used both to allow a high degree of configurability,...
Functional verification is a cornerstone of successful design, yet its complexity often poses significant challenges. In this presentation, we’ll explore some of the key verification methodologies, focusing on practical approaches that enhance efficiency and reliability. While the discussion will remain broad to resonate with a wide audience, specific topics such as testbench strategies,...
PRO DESIGN Electronic GmbH develops high-end FPGA-based solutions and proprietary hardware platforms for applications demanding maximum performance, precision, and reliability. Our in-house FPGA accelerator cards are engineered for complex, data-intensive environments such as scientific research, broadcast, and embedded computing. With decades of experience in FPGA design, high-speed...
Developing and deploying a verification methodology is costly and time consuming. Going without one is even more costly due to bugs escaping into production hardware systems.
Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM. Yet OSVVM is easier as it...
