Name: Verification with UVM for HEP Workshop
Start: 2024-11-25T09:00:00+01:00
End: 2024-11-28T17:30:00+01:00
Location: CERN

Monday 25 November
- 1
  
  Welcome
  
  Speaker: Alessandro Caratelli (CERN)
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 10:30
  
  Coffee break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 12:00
  
  Lunch break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 15:15
  
  Coffee break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
Tuesday 26 November
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 10:30
  
  Coffee break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 12:00
  
  Lunch break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 15:15
  
  Coffee break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
Wednesday 27 November
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 10:30
  
  Coffee break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 12:00
  
  Lunch break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
- 15:15
  
  Coffee break
- SystemVerilog accelerated verification using UVM
  
  Convener: Luca Brambilla (Cadence)
Thursday 28 November
- Verification best practices for HEP
- 10:30
  
  Coffee break
- Verification best practices for HEP
- 12:00
  
  Lunch break
- Verification best practices for HEP
- 15:15
  
  Coffee break
- Verification best practices for HEP

Verification with UVM for HEP Workshop

593/R-013

CERN