Speakers
Description
The Smartpixels project is a coordinated effort to co-design pixel ASICs, design tools, ML algorithms, and sensors for on-detector data reduction, motivated by the technical challenges of current and future colliders. The drive to greater precision requires smaller pixel pitch, which together with higher event rates arising from pileup and/or beam-induced background generates petabytes of data per second. Readout chips must be power-efficient, radiation-hard, and capable of real-time data processing.
The smartpixels team has developed algorithms for selecting the signatures of high-momentum tracks and coarse particle-trajectory reconstruction, and explored how the performance changes with pixel sensor geometry, orientation, and irradiation.
We have leveraged and extended hls4ml to support neural network architectures meeting the strict latency and area constraints. To target our TSMC 28nm ASIC implementations, we have integrated the flow with Catapult HLS, allowing seamless synthesis of these designs into RTL for backend integration, and our first custom pixel ASICs have been produced and are undergoing testing.
We will present the status of ongoing work, including efforts in testing ASICs, producing a new ASIC with trajectory-reconstruction algorithm, and improving the realism of the detector simulation though including noise, charge thresholds, and other effects.
