Present: Aramis, Clement, David, Dominik, Fulvio, Jonas, Nagore, Louis, Serge, Raul, Todor

Q1, Raul: Should we keep the interface of individually enabling/disabling and inverting PWM A/B outputs?

Aramis, Fulvio: They are not independent, this can cause issues.

Todor: This could be useful on test bench cases.

Final decision: PWM A/B shall always be inverted together, no individual handlers will be given for inverting only one signal. Enabling/disabling output may remain individually set for testing purposes to avoid rewiring.

Q2, Serge: There is no sawtooth carrier, only triangular?

Raul: This is what has been agreed upon. This can be added if you have a strong use-case.

Serge: It could be interesting to have the option.

Jonas, Raul: If it is only interesting, then let's keep only one carrier type, the triangular one. OK from Serge

Final decision: Only triangular carrier is provided with the PWM IP core.

Q3, Raul: Can the update type change during run-time or is it fixed at configuration?

No need voiced for run-time flexibility.

Final decision: Update type shall be a configuration parameter and will not be modifiable at run-time.

Q4, Fulvio: What strategies are in place to ensure that experts don't make mistakes in configuration?

Aramis: this must be more robust than a GUI layer of the Configurator.

Raul: Yes, but this protection is being designed by David Nisbet, and is a discussion for a separate meeting.

Final decision: To be discussed later.

Q5, Raul: What should happen if minimum time on/off is violated at the 2nd level in VHDL? 

There is a layer of protection in software, VHDL: they both need to fail before comes to this. This code should never be executed in principle. Default: raise a fault and trip converter as gracefully as possible.

Todor: This check should be implemented as a counter for comparison with the setting.

Serge: The check should be placed later on, by checking the final output.

Aramis: This behaviour needs to be well documented.

Final decision: Move the check to the final output, document the behaviour.

Q6, David: Is there tolerance for clipping in software?

Dominik: The clipping will be done at numerical precision

Raul: In FPGA, the counters's precision will be 2.5 ns for min on/off time protection

Q7, Raul: We have heard that the unipolar full bridge is not commonly used and don't have the track who requested it. Who uses this full bridge?

Nagore, Louis: LPC does.

Q8, Raul: How do you wire the bipolar full bridge? We are concerned that the complementary of leg 2 may not be exactly the same as PWMA of leg 1 due to dead time delays. If they are wired such that PWMB is swapped with PWMA on leg 2 this could be ensured.

Todor: The dead time is just a protection. This is not a problem right now and shouldn't be in the future.

Serge: We may not use full-bridges at all, as using half-bridges directly gives us more flexibility.

Jonas: Presented how the PWMA of leg 1 will be equal to PWMB of leg 2, even with dead time.

Final decision: no special wiring or use scheme is necessary to ensure consistency.