Speaker
Description
One of the main challenges of picosecond TDC for 4D pixel detectors at future hadron colliders is the limitations of power consumption (down to $\mu$W/channel). To significantly reduce the power consumption and maintain other key specifications such as trigger rate and time resolution, a two-stage time-stretching TDC is proposed. This talk will present the proof-of-concept prototype design and testing of such TDC with discrete components (such as SMT transistors and capacitors). Time resolution of better than 100 ps is achieved with a 100 MHz clock, making it a stepping-stone towards future ASIC design with modern CMOS technology.
Summary (500 words)
Tracking and event reconstruction for particle experiments at future hadron-hadron colliders (such as HL-LHC, FCC-hh) will face unprecedented challenges due to the very high density of particles per collision event. Tackling such challenges requires many technological innovations, and the essential requirement is precision timing ability on multiple detectors, including tracking. The requirement relies on < 50 ps timing resolution on both the sensor and readout electronics for the tracking detector, while simultaneously imposing stringent requirements on power consumption, radiation hardness, pitch size, event rate, etc. Among all the challenges, a solution for 4D pixel readout ASIC with uW/channel power consumption and less than 50 ps time resolution does not exist in the market yet.
One option to achieve super low power consumption in high-precision TDC is to use time-stretching. A time-stretching TDC is based on capacitor charging and discharging, which amplifies the width of the measured pulse and makes it possible to achieve high resolution with slow clock counter, which will significantly reduce the power consumption.
The main challenge of such TDC, however, is the large deadtime it introduces due to time-stretching, making it difficult to deal with high hit rate such as about 100kHz/pixel at HL-LHC. A two-stage time-stretching design is proposed in this talk to reduce the conversion time, where the input pulse with width W is first amplified by a factor of N, and measured with a low-speed clock counter. After counting, the tail of the amplified pulse is amplified again by a factor of N and measured with the same counter. By doing so, a factor of NN amplification is achieved with a deadtime of only 2NW (instead of NNW).
Design and optimization of such TDC requires a lot of optimizations in the circuit parameters, such as the choice of counter clock speed and the stretching factors of each stage, the design of the time-stretching unit (capacitor and charging currents), etc. To fully study the behavior of such circuits and perform fast optimizations at low cost, a prototype TDC made with commercially available discrete SMT components (such as SMT transistors and capacitors) is presented.
The prototype TDC is tested to achieve less than 100 ps time resolution with a 100 MHz clock counter on low power and low-cost FPGA (a factor of more than 100-time amplification). The deadtime is less than 200 ns for a 10 ns input range. An onboard calibration system comprised of a pulse generation circuit is implemented and calibration results are presented. The system can be used as a test and optimization platform towards the ASIC implementation of the TDC for future 4D pixel detectors with the goal of less than 50 ps resolution and uW/channel level power consumption. The system can also be used as modular electronics for a low-cost solution for a TDC with 100 ps level precision in various particle experiments, such as photoelectron timing extraction circuit for photo-detector readout in neutrino experiments.