6th 28 nm Mixed-Signal Design Workshop

Name: 6th 28 nm Mixed-Signal Design Workshop
Start: 2025-03-24T09:00:00+01:00
End: 2025-03-28T17:30:00+01:00
Location: Remote

24 Mar 2025, 09:00 → 28 Mar 2025, 17:30 Europe/Zurich

Remote

CERN EP-ESE, CERN ICs Design and Technology Support

From the same series

1 2 3 4 5 6 8

Contacts

asic.support@cern.ch

Registration

28nm Mixed-Signal Design - REGISTRATION

28nm Mixed-Signal Design - WAITING LIST

Surveys

Workshop on 28nm design survey

67261226068

Marco Andorno

Alessandro Caratelli, Wojciech Bialas

Join via phone

Monday 24 March
- 09:00 → 10:30
  Overview of the 28nm technology
  - 09:00
    
    Welcome 20m
    
    Speaker: Alessandro Caratelli (CERN)
  - 09:20
    
    Technology Overview and designer’s guidelines 40m
    
    Speaker: Alessandro Caratelli (CERN)
  - 10:00
    
    Overview of the 28nm common design platform 30m
    
    Speaker: Marco Andorno (CERN)
- 10:30 → 10:45
  
  Coffee break 15m
- 10:45 → 12:00
  Overview of the 28nm technology
  - 10:45
    
    Total Ionizing Dose response of the 28nm technlogy 1h 15m
    
    Speaker: Giulio Borghello (CERN)
- 12:00 → 13:30
  
  Lunch break 1h 30m
- 13:30 → 15:15
  Analog design
  - 13:30
    
    Analog simulation with Explorer and Assembler 20m
    
    Speaker: Helga Uchoa Dornelas
  - 13:50
    
    Lab session (Analog simulation) 1h 25m
    
    Speaker: Helga Uchoa Dornelas
- 15:15 → 15:30
  
  Coffee break 15m
- 15:30 → 17:30
  Mixed-signal design
  - 15:30
    
    Mixed-signal simulation with Xcelium and Virtuoso 30m
    
    Speaker: Helga Uchoa Dornelas
  - 16:00
    
    Lab session (Mixed-signal simulation) 1h 30m
    
    Speaker: Helga Uchoa Dornelas
Tuesday 25 March
- 09:00 → 10:30
  Mixed-signal design
  - 09:00
    
    Lab session (Mixed-signal simulation) 1h 30m
    
    Speaker: Helga Uchoa Dornelas
- 10:30 → 10:45
  
  Coffee break 15m
- 10:45 → 12:00
  Analog design
  - 10:45
    
    Analog Backend VXL Best Practices 15m
    
    Speaker: Philippe Carriere (Cadence)
  - 11:00
    
    Lab session (Analog backend) 1h
    
    Speaker: Philippe Carriere (Cadence)
- 12:00 → 13:30
  
  Lunch break 1h 30m
- 13:30 → 14:45
  Analog design
  - 13:30
    
    Lab session (Analog backend) 1h 15m
    
    Speaker: Philippe Carriere (Cadence)
- 14:45 → 15:00
  
  Coffee break 15m
- 15:00 → 15:50
  Mixed-signal design
  - 15:00
    
    Abstract generation 20m
    
    Speaker: Philippe Carriere (Cadence)
  - 15:20
    
    Lab session (Abstract) 30m
    
    Speaker: Philippe Carriere (Cadence)
- 15:50 → 17:30
  Analog design
  - 15:50
    
    DRC/LVS with PVS 20m
    
    Speaker: Philippe Carriere (Cadence)
  - 16:10
    
    Lab session (DRC/LVS with PVS) 1h 20m
    
    Speaker: Philippe Carriere (Cadence)
Wednesday 26 March
- 09:00 → 10:00
  Mixed-signal design
  - 09:00
    
    IP block integration (Liberty file and Abstract) 15m
    
    Speaker: Marco Andorno (CERN)
  - 09:15
    
    Lab session (Liberty file) 45m
    
    Speaker: Marco Andorno (CERN)
- 10:00 → 10:15
  
  Coffee break 15m
- 10:15 → 12:30
  Digital design
  - 10:15
    
    Digital flow introduction 30m
    
    Main steps of the flow, tools, Flowkit
    
    Speakers: Mohamed Naeim (Cadence Design Systems), sebastien porte
  - 10:45
    
    Single event effects hardening in digital design 45m
    
    Speaker: Alessandro Caratelli (CERN)
  - 11:30
    
    Lab session (TMR) 1h
    
    Speakers: Alessandro Caratelli (CERN), Marco Andorno (CERN)
- 12:30 → 13:30
  
  Lunch break 1h
- 13:30 → 15:15
  Digital design
  - 13:30
    
    Timing constraints and synthesis 1h 45m
    
    Speakers: Mohamed Naeim (Cadence Design Systems), sebastien porte
- 15:15 → 15:30
  
  Coffee break 15m
- 15:30 → 17:30
  Digital design
  - 15:30
    
    Lab session (Synthesis and LEC) 2h
    
    Speakers: Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte
Thursday 27 March
- 09:00 → 10:15
  Digital design
  - 09:00
    
    Block-level implementation 1h 15m
    
    Synthesis, floorplan
    
    Speakers: Mohamed Naeim (Cadence Design Systems), sebastien porte
- 10:15 → 10:30
  
  Coffee break 15m
- 10:30 → 12:00
  Digital design
  - 10:30
    
    Block-level implementation 1h 30m
    
    Placement, clock tree synthesis, routing
    
    Speakers: Mohamed Naeim (Cadence Design Systems), sebastien porte
- 12:00 → 13:30
  
  Lunch break 1h 30m
- 13:30 → 14:45
  Digital design
  - 13:30
    
    Lab session (Block-level implementation) 1h 15m
    
    Speakers: Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte
- 14:45 → 15:00
  
  Coffee break 15m
- 15:00 → 17:30
  Digital design
  - 15:00
    
    Lab session (Block-level implementation) 2h 30m
    
    Speakers: Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte
Friday 28 March
- 09:00 → 10:15
  Digital design
  - 09:00
    
    Hierarchical implementation 1h 15m
    
    Top level analysis with use of block model, assemble design
    
    Speakers: Mohamed Naeim (Cadence Design Systems), sebastien porte
- 10:15 → 10:30
  
  Coffee break 15m
- 10:30 → 12:00
  Digital design
  - 10:30
    
    Lab session (Hierarchical implementation) 1h 30m
    
    Speakers: Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte
- 12:00 → 13:30
  
  Lunch break 1h 30m
- 13:30 → 15:00
  Digital design
  - 13:30
    
    Signoff 1h 30m
    
    Timing analysis, power analysis, DRC, LVS
    
    Speakers: Mohamed Naeim (Cadence Design Systems), sebastien porte
- 15:00 → 15:15
  
  Coffee break 15m
- 15:15 → 17:30
  Digital design
  - 15:15
    
    Lab session (Signoff) 2h 15m
    
    Speakers: Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte