Joint ECF & RAWG Meeting: Reliable Gateware

Thursday 13 Feb 2025, 09:00 → 10:50 Europe/Zurich

774/1-079 (CERN)

774/1-079

CERN

20

Show room on map

67541821230

Lukas Felsberger

- 1
  
  Introduction
  
  Speaker: Mathieu Saccani (CERN)
  
  2025-02-13-Reliable_gateware_intro.pdf
  
  2025-02-13-Reliable_gateware_intro.pptx
- 2
  
  HSE/RP
  
  Reliability is crucial for safety-critical systems like CROME. In this presentation, I’ll walk through the different methods our team uses to keep our gateware code as bug-free as possible. We’ll cover directed tests, Python/HDL co-simulation, formal verification, and full HW/SW co-simulation—discussing their strengths, weaknesses, and what works best for a small teams such as ours at CERN.
  
  Speaker: Clyde Laforge (CERN)
  
  HSE_RP_IL_ReliableGateware.pdf
  
  HSE_RP_IL_ReliableGateware.pptx
- 3
  
  TE/MPE
  
  Development flow and tools on an example project
  Focus on Standard IEC62566
  
  Speaker: Antoine Colinet (CERN)
  
  20250213_firmware_reliability.pdf
  
  20250213_firmware_reliability.pptx
- 4
  
  SY/EPC
  
  Development flow and tools on an example project
  Focus on the methodology used in EPC (example project)
  
  Speakers: Adrian Byszuk (CERN), Valerio Nappi
- 5
  
  SY/BI
  
  Gateware verification flow for the BLM LHC processing FPGA
  Focus on tools (CI, linter, cheby, VUNIT, HDLmake, script for requirement, documentation…)
  
  Speaker: Konstantinos Blantos
  
  ecf_rawg_reliable_gw.pdf
- 6
  
  Discussion