For the D1.1 (15-layer prototype):

1. The building of the first 2 layers done in IFIC, taught us:
1. that we should cure the conductive glue at lower temperature to avoid bending the PCB
2. we should slightly modify the design and order as soon as possible the HV Kapton
2. Their commissioning have shown very good performances:
1. very few masked channels (≤0.5%, outside the faulty ASIC), even without a full fledged optimization of thresholds (individual cell adjustments).
2. S/N ration in the readout branch ~ 30, with moderate gain, which is comparable as the best measures of seen before.
3. The mechanical handling will probably need a slight adjustment.

So no show stopper to launch the rest of the production, but at first view, we are in time to have 15 layers by the end of 2025.
This will depend heavily on the availability of the people from IFIC.

For the D2.1 (the pilote module):

1. The CALOROC1C design is complete and will soon be launch in production, we could probably test some chips in the fall.
   The claimed power consumption (10 mW/ch) are in line with the expectations.
   We should also evaluate the consumption of the ancillary components (LDO, concentrators).
2. In between, we will start thinking on how to adapt the design of the FEV and DAQ for the new ASICs, which are said to be compatible with the existing HKROC. A card based on the HKROC could be a first step.
3. The first scheme and simulations of a cold plate, show that 4 mm of Cu (replacing a part of the W), would be enough to cool a layer, with a reasonably low water flow (≤1ℓ/min). More work is needed on how to place the interfaces (together with DAQ).
4. The work on timing has started, but we still far from having any conclusions (as you know, it is our ANR).