3–5 May 2012
INFN Pisa
Europe/Paris timezone

MCM-D Technology for Silicon Strip Frontend Hybrids

4 May 2012, 09:30
30m
INFN Pisa

INFN Pisa

Largo Bruno Pontecorvo 3 56127 Pisa Italy
Development of critical technologies and system integration Development of critical technologies and system integration

Speaker

Lars Eklund (University of Glasgow (GB))

Description

Multi-chip Modules - Deposited (MCM-D) technology can be applied to silicon strip modules and promises advantages in terms of integration complexity and material budget. The principle is to deposit alternating dielectric and metal layers directly on the silicon sensor, building up a PCB like structure. With lithographic techniques traces and vias are etched with high resolution creating a circuit replacing the pitch adaptor, wire bonds and electronics hybrid. This paper reports on a feasibility study performed in the context of the Atlas Upgrade. The technology was evaluated in two prototype processing runs. The first prototypes had a single dielectric and metal layer deposited on a silicon strip sensor, with the purpose of evaluating the change in performance due to the post-processing and the presence of a ground plane. Sensor parameters were measured before and after irradiation up to 10^16 n_eq/cm^2 and charge collection efficiency was measured for several doses. A non-irradiated sensor was measured in a beam test yielding signal height and resolution for regions with and without ground plane. The second prototype was a fully functional 20-chip front-end hybrid with five metal layers build on a blank silicon sensor. The hybrid has the same performance as an identical circuit built in kapton technology.

Summary

The next generation silicon tracking detectors are tending to a higher
density of read-out channels over a large area. Hence an increased
level of integration of the detector modules is desirable. Multi-chip
Modules - Deposited (MCM-D) technology applied to silicon strip
modules and promises advantages in terms of integration complexity and
material budget. The principle is to deposit alternating dielectric
and metal layers directly on the silicon sensor, building up a PCB
like structure. With lithographic techniques traces and vias are
etched with high resolution creating a circuit replacing the pitch
adaptor, wire bonds and electronics hybrid.

The features sizes possible are smaller compared to traditional PCB
technologies. Minimum track width and spacing is in the order of 10-30
um and vias are in the order of 50 um. Layer thicknesses are typically
3-15 um for dielectric layers and 1-3 um for metal layers.

This paper reports on a feasibility study performed in the context of
the Atlas Upgrade. The technology was evaluated in two prototype
processing runs performed by a semi-industrial partner (Acreo,
Norrkoping, Sweden). The first prototypes had a single dielectric and
metal layer deposited on a silicon strip sensor, with the purpose of
evaluating the change in performance due to the post-processing. The
design had via-connections to the strip pads and different types of
ground planes covering the sensor area. This corresponds to the first
layer of processing in a full design, hence giving the bulk of the
change in performance of the sensor.

Sensor parameters such as I/V, C/V, C_is and R_is were measured for
non-irradiated samples and for an array of doses up to 10^16
n_eq/cm^2. Charge collection efficiency was also measured for the same
doses. A non-irradiated sensor was measured in a beam test yielding
signal height and resolution for regions with and without ground
plane.

The second prototype was a fully functional 20-chip front-end hybrid
with five metal layers build on a blank silicon sensor. The hybrid is
digitally fully functional and shows the same analogue performance
parameters (noise, gain, stability) as an identical circuit built in
kapton technology.

Primary author

Lars Eklund (University of Glasgow (GB))

Co-authors

Alexandre Chilingarov (Lancaster University (GB)) Ashley Greenall (University of Liverpool (GB)) Daniel Hynds (University of Glasgow (GB)) Gianluigi Casse (University of Liverpool (GB)) John Matheson (STFC - Science & Technology Facilities Council (GB)) Dr Tony Affolder (University of Liverpool (GB))

Presentation materials