May 27 – 29, 2026
CERN
Europe/Zurich timezone
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KalEdge-Lite: Hardware-Aware ML-to-FPGA Deployment with Automated hls4ml Integration

May 28, 2026, 11:45 AM
20m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
Show room on map
Talk Algorithm implementation in HDL and HLS AI

Speaker

Romina Soledad Molina (kaleidoforge)

Description

KalEdge-Lite is a hardware-aware framework that automates neural network deployment on FPGA platforms through an end-to-end ML-to-bitstream workflow. The system integrates model training, compression techniques, hardware-aware evaluation, and automated accelerator generation. A regime-aware analytical model estimates FPGA resource utilization and latency before synthesis, enabling rapid identification of hardware-feasible configurations without repeated HLS execution. KalEdge-Lite supports multiple FPGA platforms and enables reproducible deployment from trained models to validated hardware implementations. The presentation will demonstrate practical deployment workflows and discuss experience using automated hardware-aware configuration screening for FPGA-based neural network acceleration.

Talk's Q&A During the talk
Talk duration 15'+7'
Will you be able to present in person? Yes
If we are unable to accommodate your oral presentation, would you be willing to consider presenting a poster instead? Yes

Author

Romina Soledad Molina (kaleidoforge)

Presentation materials