Speaker
Description
This talk demonstrates that adopting DevOps principles for FPGA projects is neither complex nor prohibitively expensive. Using widely available open-source tools, mature software-style pipelines can be applied to hardware design with meaningful productivity gains.
The presentation will cover a practical end-to-end approach, including:
- Effective use of Git-based version control for HDL, constraints, IP cores, and testbenches
- Automated CI pipelines for synthesis, place-and-route, and bitstream generation
- Testing via simulation
- Hardware-in-the-loop (HIL) validation using FPGA boards with CI runners
- Automated firmware loading, test execution, and result reporting for closed-loop verification
The talk concludes with a concrete industrial case study: the ASIC prototyping phase of an edge AI audio processing device.
| Talk's Q&A | During the talk |
|---|---|
| Talk duration | 25'+12' |
| Will you be able to present in person? | Yes |
| If we are unable to accommodate your oral presentation, would you be willing to consider presenting a poster instead? | No |